Apparatus and method for wideband communication with suppression of harmonic interference

• US 4,109,204 A
• Filed: 12/29/1976
• Issued: 08/22/1978
• Est. Priority Date: 12/29/1976
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Stutt, Charles A., Kincaid, Thomas G.
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US05/755,614
• Time in Patent Office: 601 Days
• Field of Search: 325/39, 325/40, 325/43, 325/44, 325/52, 325/141, 325/143, 325/164, 178/53, 178/68, 178/69.1, 340/167 R, 340/310 R, 340/310 A, 179/15 BL, 331/1 R, 331/19, 358/12, 358/13
• US Class Current: 375/285
• CPC Class Codes: H04B 14/02 characterised by the use of pulse modulation in radio transmission relays H04B7/17
• CPC Class Codes: H04B 2203/5416 by adding signals to the wave form of the power source
• CPC Class Codes: H04B 2203/542 using zero crossing information
• CPC Class Codes: H04B 2203/5425 improving S/N by matching impedance, noise reduction, gain control
• CPC Class Codes: H04B 2203/5466 using three phases conductors
• CPC Class Codes: H04B 2203/5483 using coupling circuits
• CPC Class Codes: H04B 3/542 the information being in digital form

Abstract

A method for transmitting information with a desired bandwidth while suppressing interference due to harmonics of a system-wide signal, by transmitting each bit of information as a pair of spaced rectangular envelope modulation pulses having a time interval therebetween essentially equal to the reciprocal of the difference between the frequencies of a carrier and of adjacent harmonics of the undesired system-wide signal. A sequential plurality of double-pulse modulating waveforms can be transmitted for reception by a receiving means having a like plurality of demodulators each synchronized and sequentially enabled only when one of the pair of modulating pulses are present. A novel double-pulse demodulator means, capable of essentially rejecting undesirable harmonics in a system utilizing a data carrier modulated to be interlaced between sequential harmonics of a system-wide signal, and novel means for synchronous gating thereof, are disclosed.

Claims

1. A method for transmitting information with a desired bandwidth while suppressing interference thereto from harmonics of a system-wide signal, comprising the steps of:

(a) providing a data carrier having a frequency essentially midway between an adjacent pair of harmonics of the system-wide signal;

(b) transforming each of a plurality of bits of the information into a signal comprising a pair of like-polarity pulses, each pulse having a time duration T;

(c) setting a time interval P between the pair of pulses to be essentially equal to twice the reciprocal of the frequency difference between the frequency of the data carrier and the frequency of the adjacent harmonics of the system-wide signal;

(d) modulating one of the parameters of the data carrier with the pulse-pair signal to be transmitted;

(e) transmitting the modulated data carrier to a receiving end; and

(f) detecting the pulse-pair signal to recover at the receiving end each bit of data therein.

2. A method as set forth in claim 1, wherein each of the pair of pulses is a rectangular pulse.

3. A method as set forth in claim 1, wherein step (b) includes the step of setting the time duration T of each pulse to be essentially equal to the inverse of a selected integer multiple of the frequency difference between the frequency of the data carrier and the frequency of each of the adjacent harmonics of the system-wide signal.

4. A method as set forth in claim 1, wherein step (d) includes the step of varying the amplitude of both pulses of the pair equally in accordance with the value of each bit of information.

5. A method as set forth in claim 1, wherein step (d) includes the step of varying the phase of the data carrier by equal amounts and polarities during each of the pulses of the pair in accordance with the value of each bit of information.

6. A method as set forth in claim 1, wherein information is transmitted in binary form and step (d) includes the step of varying the polarity of both pulses of the pair in accordance with a binary value of each information bit.

7. A method as set forth in claim 1, further comprising the steps of:

sequentially arranging an integral number M of bits of data for sequential transmission as a frame of modulation on said data carrier, each bit of data being transformed to one of said signals comprising a pair of spaced pulses;

sequentially transmitting the first pulse associated with each of the M sequential data bits prior to sequentially transmitting the second pulse associated with each of the M data bits; and

generating each of the pulses with a time duration T essentially equal to the quotient of the time interval P between first and second pulses of a pair and the number of bits to be sequentially transmitted in the associated frame.

8. A method as set forth in claim 7, further comprising the steps of providing the receiving end with a plurality M of data detector means, equal in number to the number M of information bits transmitted in a frame;

and sequentially enabling each of the data detector means to receive each pulse of only that one of the plurality M of pulse-pairs assigned to an individual one of said plurality of detector means to decode each sequential bit of the modulation on said data carrier.

9. A method as set forth in claim 8, further comprising the steps of:

transmitting a synchronization code prior to the at least one information frame of a message;

acquiring the synchronization code at said receiving end; and

synchronizing the enablement of each of said plurality of data detector means responsive to receipt of said synchronization code.

10. A method as set forth in claim 9, wherein said systemwide signal is of a multi-phase nature, and further comprising the step of synchronizing said plurality of detector means both to said synchronization code and to a selected phase of the multiple-phase system-wide signal, whereby the modualtion of the data carrier is detected even in the presence of shift of the phase of the system-wide signal.

12. Apparatus as set forth in claim 1, wherein said detector means further comprises second switch means operable responsive to said second switching signal to return said first means to a preselected set of initial conditions.

13. Apparatus as set forth in claim 12, further comprising means receiving said first switching signal for generating an output responsive to the cessation of every other occurrence of said first switching signal, said output being said second switching signal.

14. Apparatus as set forth in claim 13, further comprising means for limiting said second switching signal to be active only for a preselected time duration.

11. Apparatus for receiving information transmitted as a plurality of bits of information, each bit modulating a data carrier having a carrier frequency essentially interlaced midway between a pair of adjacent harmonics of a system-wide signal, with a pair of like-polarity signal pulses having a pulse duration T and a time interval P between pulses, comprising:

means for receiving the modulated data carrier;

demodulator means for recovering the pulse-pair modulation signal from the modulated data carrier;

detector means receiving the pulse-pair modulated signal for recovering the value of the bit of information responsive to both pulses of a modulation signal, said detector means comprising input means for receiving the pulse-pair modulation signal;

first means for integrating the amplitude of said signal;

first switch means for coupling said signal to said first means responsive to said first switching signal present essentially only when one of said pair of pulses should be present at said input means;

second means for storing the amplitude of the integrated signal responsive to a second switching signal present only after every other occurrence of said first switching signal; and

output means at which the amplitude stored in said second means appears as the recovered value of the associated bit of information; and

means for synchronizing said detector means to operate only when each of said pair of pulses of a modulation signal is present.

15. Apparatus for receiving information transmitted as a plurality of bits of information, each bit modulating a data carrier having a carrier frequency essentially interlaced midway between a pair of adjacent harmonics of a system-wide signal, with a pair of like-polarity pulse signals having a pulse duration T and time interval P between pulses, comprising:

means for receiving the modulated data carrier;

demodulator means for recovering the pulse-pair modulation signal from the modulated data carrier;

detector means receiving the pulse-pair modulated signal for recovering the value of the bit of information responsive to both pulses of a modulation signal; and

means for synchronizing said detector means comprising

clock means having an output at a clock frequency essentially equal to the reciprocal of the time interval P between pulses;

means for generating a pulse of duration T at the essentially identical point during each cycle of the output of said clock means to generate said first switching signal; and

third means coupled to said demodulator means for synchronizing said clock means to cause said first switching signal to be present essentially in synchronism with each one of said pair of pulses.

16. Apparatus as set forth in claim 15, wherein said time interval P is established essentially equal to the reciprocal of the frequency of said system-wide signal;

said clock means including oscillator means;

means for detecting the frequency of a multiplicity of zero crossings of said system-wide signal; and

means locking the frequency of said oscillator means to the frequency of said zero crossings.

17. Apparatus as set forth in claim 15, wherein said third means comprises:

means for producing pulses at a first frequency equal to the reciprocal of twice the time interval P;

means for locking said first frequency to the frequency of a synchronization code pattern transmitted immediately prior to transmission of a message containing at least one pulsepair signal; and

fourth means enabling the output of said clock means only when said first frequency is locked to said synchronization frequency.

18. Apparatus as set forth in claim 17, wherein said clock means comprises oscillator means having an output frequency at an integer multiple K of said clock frequency;

divider means having a reset input for generating an output signal for every K cycles of said oscillator means output frequency only after a first state is established as said reset input, the output of said divider means being disabled when a second state is established at said reset input; and

said fourth means comprises means for detecting a first one of a plurality of transitions of said synchronization code pattern after said first frequency is locked thereto; and

means for generating said first state at said reset input of said divider means immediately after said first transition is detected.

19. Apparatus as set forth in claim 18, further comprising means for disconnecting said third means from said demodulator means after said first state is generated;

said fourth means being adapted to maintain said first state at said reset input for a substantially fixed time interval at least as long as the expected duration of a message.

20. Apparatus as set forth in claim 18, wherein an integer number M of bits of data are sequentially transmitted as a frame of modulation on said data carrier, each bit of data being transformed to an associated pulse-pair signal with each pulse having a pulse time duration T essentially equal to the quotient of the time interval P between first and second pulses of a pair and the number M of data bits per frame;

said M pulse-pairs being transmitted in said frame with sequential transmission of each of the M first pulses prior to the sequential transmission of each of the M second pulses of sequentially similar ones of the pulse-pairs;

said apparatus further comprising (M-1) additional detector means, each receiving the pulse-pair modulation signal from said demodulator means;

said synchronizing means including means for providing each of the M detector means with first and second switching signals having proper timing for recovering each sequential one of the values of the M sequential data bits of a frame at the output means of the associated detector means; and

means for sequentially coupling each detector means output means to a common detector output to obtain the recovered data bit values in proper sequential order.

21. Apparatus as set forth in claim 20, wherein the clock means output frequency is established to be M times the reciprocal of the time interval P, and further comprising counter means receiving said clock means output frequency for generating M independent sequentially and cyclically enabled outputs, each of said M outputs being the first switching signal for an associated one of the M detector means.