Digital demodulator-correlator

• US 4,112,497 A
• Filed: 03/29/1977
• Issued: 09/05/1978
• Est. Priority Date: 03/29/1977
• Status: Expired due to Term

• Current Assignee: Arthur I. Zygielbaum, Fletcher James C Administrator of The National Aeronautics and Space Administration With Respect To An Invention of, James W. Layland, Richard M. Goldstein, Warren L. Martin, William P. Hubbard
• Original Assignee: Arthur I. Zygielbaum, Fletcher James C Administrator of The National Aeronautics and Space Administration With Respect To An Invention of, James W. Layland, Richard M. Goldstein, Warren L. Martin, William P. Hubbard
• Inventors: Goldstein, Richard M., Fletcher, James C. Administrator of the National Aeronautics and Space administration, with respect to an invention of, Layland, James W., Hubbard, William P., Zygielbaum, Arthur I., Martin, Warren L.
• Primary Examiner(s): Gruber, Felix D.
• Application Number:
  US05/782,464
• Time in Patent Office: 525 Days
• Field of Search: 328/133, 328/134, 329/50, 329/112, 329/122, 343/6.5 R, 343/12 R, 343/14, 364/456, 364/458, 364/459, 364/728, 364/604, 364/819
• US Class Current: 708/422
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00

Abstract

Apparatus for demodulation and correlation of a code modulated 10 MHz signal is comprised of a sample and hold analog-to-digital (A/D) converter synchronized by a frequency coherent 40 MHz pulse to obtain four evenly spaced samples A1,B1,A2 and B2 of each cycle of the signal, and means for adding, or subtracting, each sample to, or from, one of four accumulators to form the sums: ##EQU1## where M1 = 10 MHz Reference · Receiver Code ∠0°

M2 = 10 mhz Reference · Receiver Code ∠90°

The correlation functions that are used for the range measurements are then computed from the following equations:

I = S1.sub.I cos α - S2.sub.I sin α

Q = S1.sub.Q cos α - S2.sub.Q sin α

where sin α and cos α are determined at the start of each range acquisition by forcing the receiver code for both M1 and M2 to be equal to 1 and applying these equations: ##EQU2##

Claims

1. Apparatus for demodulation of a code modulated signal having a predetermined frequency and for correlation of the demodulated signal with a reference code, comprising

means for sampling said code modulated signal at a frequency four times said predetermined frequency and for converting each sample to digital form, thereby to produce four equally spaced successive samples A1, B1, A2 and B2 in digital form for each cycle of said modulated signal,

four separate means for accumulating multiplication products of M1 and M2 with said samples in digital form thereby to produce four sums according to the following equations:

##EQU17## where M1 is a reference signal at said predetermined frequency multiplied by said reference code, and M2 is said reference signal multiplied by said reference code delayed one quarter of a cycle,

means for computing inphase and quadrature correlation functions I and Q, respectively, from said sums in accordance with the following equations;

space="preserve" listing-type="equation">I = S1.sub.I cos α

- S2.sub.I sin α

space="preserve" listing-type="equation">Q = S1.sub.Q cos α

- S2.sub.Q sin α

where sin α and

cos α

are determined at the start of demodulation operations according to the following equations;

##EQU18## while both multipliers M1 and M2 are made to be equal to said reference signal, and

means for making both multipliers M1 and M2 equal to said reference by setting said reference code and said reference code delayed one quarter of a cycle equal to 1 at the start of demodulation and correlation operations while sin α and

cos α

are being determined.

2. Apparatus as defined in claim 1 wherein said means for sampling said code modulated signal is comprised of means for multiplying said reference signal by four and means responsive to the resulting higher frequency signal for timing the samples so that said four equally spaced samples all occur at the same phases on successive cycles of the code modulated signal.

3. Apparatus as defined in claim 2 wherein said four separate means for accumulating samples in digital form are synchronized by a timing signal at half the frequency of said higher frequency signal, and means responsive to said timing signal for routing samples A1 and A2 to both means for accumulating the sums S1_I and S1_Q, and means responsive to the complement of said timing signal for routing samples B1 and B2 to both means for accumulating the sums S2_I and S2_Q.

4. Apparatus as defined in claim 3 wherein said timing signal, and its complement, and said higher frequency signal, are coherently produced by said frequency multiplying means from said reference signal to maintain phase coherence of all sampling and accumulating operations with respect to said four samples of each cycle of said code modulated signal.

5. Apparatus for demodulation of a code modulated signal having a predetermined frequency, and for correlation of the demodulated signal with a reference code, comprising

means for sampling said code modulated signal at a frequency four times said predetermined frequency in response to a sampling control signal, said sampling means including means for converting each sample to digital form,

means responsive to a reference signal at said predetermined frequency for producing said sampling control signal so that four equally spaced samples A1, B1, A2 and B2 all occur at the same phases of successive cycles of said code modulated signal, and

means for accumulating multiplication products of M1 and M2 with said samples in digital form in two pairs to form the difference of samples A1 and A2, and the difference of samples B1 and B2 in each of two channels by adding or subtracting each successive sample in accordance with a first multiplier M1 comprised of the product of a reference code and a squarewave signal at said predetermined frequency, and a second multiplier M2 comprised of the product of said reference code delayed one quarter of a cycle of said squarewave signal to form four sums according to the following equations:

##EQU19## and means for computing inphase and quadrature correlation functions I and Q, respectively, from said sums in accordance with the following equations;

space="preserve" listing-type="equation">I = S1.sub.I cos α

- S2.sub.I sin α

space="preserve" listing-type="equation">Q = S1.sub.Q cos α

- S2.sub.Q sin α

where sin α and

cos α

are determined at the start of demodulation and correlation operations according to the following equations;

##EQU20## while said reference code and said reference code delayed are both set equal to one.

6. Apparatus as defined in claim 5 wherein each of said first and second multipliers are further comprised of a squarewave chopper signal of low frequency such that each chopper cycle spans a number of cycles of said code modulated signal.

7. Apparatus for demodulation and correlation of a binary code modulated signal with a reference binary code, said signal being at a predetermined frequency greater than the pulse rate of said binary code, comprising

means for sampling said code modulated signal at four equally spaced intervals of each cycle of said code modulated signal, and for converting each sample to digital form, whereby four samples A1, B1, A2 and B2 in digital form are obtained at the same phases of said code modulated signal during successive cycles,

means for accumulating products of M1 and M2 with said samples to form four separate sums S1_I, S2_I, S1_Q and S2_Q according to the following equations:

##EQU21## where M1 is the product of a reference signal at the same frequency as said code modulated signal and said reference code, and M2 is the product of said reference signal and of said reference code delayed one quarter of a cycle of said reference signal, and

means for computing inphase and quadrature correlation functions I and Q in accordance with the following equations;

space="preserve" listing-type="equation">I = S1.sub.I cos α

- S2.sub.I cos α

space="preserve" listing-type="equation">Q = S1.sub.Q cos α

- S2.sub.Q sin α

where sin α and

cos α

are determined in advance by forcing said reference code to 1 for both multipliers M1 and M2 while producing said sums and computing ##EQU22##

8. Apparatus as defined in claim 7 wherein each of said multipliers M1 and M2 is a product of a squarewave chopper signal in addition to said reference signal and said reference code, and said chopper is of a low frequency so that each cycle spans a number of cycles of said reference code.

9. Apparatus as defined in claim 7 wherein said means for sampling said code modulated signal is comprised of means for multiplying said reference signal by four and means responsive to the resulting higher frequency signal for timing the samples so that said four equally spaced samples occur at the same phases on successive cycles of the code modulated signal.

10. Apparatus as defined in claim 9 wherein said means for accumulating products is synchronized by a timing signal at half the frequency of said higher frequency signal, and means responsive to said timing signal for routing samples A1 and A2 to form the separate sums S1_I and S1_Q, and means responsive to the complement of said timing signal for routing samples B1 and B2 to form the separate sums S2_I and S2_Q.

11. Apparatus as defined in claim 10 wherein said timing signal, and its complement, and said higher frequency signal, are coherently produced by said frequency multiplying means from said reference signal to maintain phase coherence of all sampling and accumulating operations with respect to said four samples of each cycle of said code modulated signal.

12. Apparatus as defined in claim 11 wherein said means for accumulating products is comprised of two arithmetic units and four accumulators, one arithmetic unit for both sums S1_I and S2_I under control of said multiplier M1 and one arithmetic unit for both sums S1_Q and S2_Q under control of said multiplier M2 with routing of each sample to be added or subtracted to each of two paired sums S1_I and S1_Q under control of timing signal and to each of two paired sums S2_I and S2_Q under control of the complement of said timing signal.