Conditional bypass of error correction for dual memory access time selection

• US 4,112,502 A
• Filed: 07/18/1977
• Issued: 09/05/1978
• Est. Priority Date: 10/18/1976
• Status: Expired due to Term

• Current Assignee: Sperry Rand Corporation
• Original Assignee: Sperry Rand Corporation
• Inventors: Scheuneman, James Herman
• Primary Examiner(s): Thomas, James D.
• Application Number:
  US05/817,081
• Time in Patent Office: 414 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/312, 364/303.3, 365/200
• US Class Current: 714/5.1
• CPC Class Codes: G06F 11/1052 Bypassing or disabling error detection or correction
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence

Abstract

A method of and an apparatus for conditionally bypassing the error correction function of a large scale integrated (LSI) semiconductor random access memory (RAM) is disclosed. A content addressable memory (CAM) is utilized to store the addresses of the addressable locations in the RAM in which an error was previously detected, and on each memory reference both the CAM and the RAM are simultaneously referenced by the same address. Upon a memory reference, the read data from, i.e., the date read out of, the RAM is concurrently coupled directly to an Interface Register and directly to the error detection and correction circuitry (ECC) and thence to the Interface Register. If the CAM does not contain the address, the read data that is coupled to the Interface Register is gated out at a first relatively early gate pulse. However, if the CAM does contain the address, the corrected read data from the ECC is then gated out of the Interface Register at a second relatively later gate pulse. Thus, when no error exists in the read data, the RAM is accessed at a relatively fast access time while, if an error exists in the read data, the RAM is accessed at a relatively slower access time to provide the added time required by the ECC to correct the read data.

Claims

1. A method of conditionally bypassing the error correction circuitry of an error correcting memory system, comprising:

reading out the uncorrected read bits that are stored in a memory;

determining if said read out uncorrected read bits had or had not been previously corrected;

coupling said uncorrected read bits to error correction circuitry;

generating corrected read bits from said uncorrected read bits;

coupling said uncorrected read bits to gating means;

coupling said corrected read bits to said gating means;

gating said uncorrected read bits from said gating means at a relatively fast memory access time if said uncorrected read bits had not been previously corrected or, alternatively, gating said corrected read bits from said gating means at a relatively slow memory access time if said uncorrected read bits had been previously corrected.

2. A method of conditionally bypassing the error correction circuitry of an error correcting system, comprising:

coupling a memory address to a first memory;

reading out the uncorrected read bits that are stored at the addressed addressable location in said first memory;

coupling said memory address to a second memory;

determining if said memory address is stored in said second memory;

generating a Match signal if said memory address is stored in said second memory or, alternatively, generating a Match signal if said memory address is not stored in said second memory;

coupling said uncorrected read bits to error correction circuitry;

generating corrected read bits from said uncorrected read bits;

coupling said uncorrected read bits to gating means;

coupling said corrected read bits to said gating means;

gating said uncorrected read bits from said gating means in response to said Match signal at a relatively fast memory access time or, alternatively, gating said corrected read bits from said gating means in response to said Match signal at a relatively slow memory access time.

3. A method of conditionally bypassing the error correction circuitry of an error correcting memory system, comprising:

coupling a multibit memory address to an addressable memory;

reading out the uncorrected read bits that are stored at the addressed addressable location in said addressable memory;

coupling said multibit memory address to a content addressable memory;

determining if said multibit memory address is stored in said content addressable memory;

generating a Match signal if said multibit memory address is stored in said content addressable memory or, alternatively, generating a Match signal if said multibit memory address is not stored in said content addressable memory;

coupling said uncorrected read bits to error correction circuitry;

generating corrected read bits from said uncorrected read bits;

coupling said uncorrected read bits to interface registers;

coupling said corrected read bits to said interface registers;

gating said uncorrected read bits from said interface registers in response to said Match signal at a relatively fast memory access time or, alternatively, gating said corrected read bits from said interface registers in response to said Match signal at a relatively slow memory access time.