Channel skip memory system for radio receiver

• US 4,114,104 A
• Filed: 11/15/1976
• Issued: 09/12/1978
• Est. Priority Date: 11/15/1976
• Status: Expired due to Term

• Current Assignee: E F Johnson Company (JVC Kenwood Corporation)
• Original Assignee: E F Johnson Company (JVC Kenwood Corporation)
• Inventors: Denzene, Quentin S.
• Primary Examiner(s): Griffin, Robert L.
• Assistant Examiner(s): Bookbinder, Marc E.
• Application Number:
  US05/741,868
• Time in Patent Office: 666 Days
• Field of Search: 325/335, 325/453, 325/464, 325/465, 325/468, 325/469, 325/470
• US Class Current: 455/154.2
• CPC Class Codes: H03J 5/246 using electronic means H03J5/244 takes precedence

Abstract

A channel skip memory system for radio receiver having a single channel skipping switch to inhibit the radio receiver from receiving any of selected channels of a plurality of channels of predetermined frequencies while scanning repetitively those channels selected to be received. The channel skipping switch is utilized to skip, inhibit, bypass, look around, etc., any channel of a plurality of channels a listener does not wish to receive when the channel skip memory system connected between the squelch control and the oscillator of the radio receiver has stopped on a channel while scanning in the scan mode or has been stepped to a particular channel by the channel stepping switch in the manual mode by actuating the switch. If the channel skipping switch is actuated a second time when utilizing resettable memory elements on an inhibited channel in the manual mode, the channel is enabled. The channel stepping switch is not functional during the scanning mode. A received channel may be skipped in the scanning mode on the next scanning cycle by actuating the channel skipping switch while that channel is receiving a signal. In the manual mode of operation, each channel is skipped by actuating the channel skipping switch setting a memory for each channel to be skipped. When going from the manual mode to scan mode, the memory having been set determines those channels to be received and those channels to be skipped.

Claims

1. Channel skip memory system for use in a radio receiver and connected in said receiver between a squelch control and an oscillator comprising

(a) manual-scan means having a manual mode of operation and a scan mode of operation;

(b) clock means connected to said manual-scan means;

(c) means connecting said clock means to said squelch control of said radio receiver;

(d) counter means connected to said clock means and having a plurality of outputs, each of said outputs corresponding to an individual channel of a predetermined frequency;

(e) plurality of first logic means having two inputs, one of said inputs of each of said first logic means connected to each of said plurality of outputs of said counter;

(f) channel skipping means connected to the other of said inputs of each of said first logic means;

(g) plurality of memory means having two inputs, one of said inputs of each of said memory means connected to each output of said plurality of first logic means;

(h) reset means connected between said manual-scan means and the other of said inputs of each of said memory means;

(i) plurality of second logic means having two inputs, one of said inputs of each of said second logic means connected to the output of said memory means and the other of said inputs of each of said plurality of second logic means connected to each respective output of said plurality of outputs of said counter;

(j) plurality of diodes connected to each of the outputs of said plurality of second logic means, and;

(k) plurality of crystals of predetermined frequencies, one crystal per channel connected between each of said plurality of diodes and said oscillator whereby said clock means drives said counter to cyclically scan and receive seriatim each of said channels in regular sequence and a voltage differential received by said connecting means stops said clock means to receive the radio frequency signal on a particular channel scanned and whereby actuating said channel skipping means while receiving a signal on one of said plurality of channels generates a short pulse to reset said memory means for the particular channel being received so that the channel is skipped on subsequent scanning cycles.

2. Channel skip memory system of claim 1 wherein said manual-scan means comprises a single pole double throw manual-scan switch whereby said switch has a manual mode of operation position and a scan mode of operation position.

3. Channel skip memory system of claim 2 further comprising means to reset said memory means whereby said manual-scan switch when switched from a scan position to a manual position resets all of said plurality of memory means simultaneously.

4. Channel skip memory system of claim 1 wherein said clock means comprises an astable multivibrator.

5. Channel skip memory system of claim 4 wherein said astable multivibrator comprises two end-coupled NAND logic gates.

6. Channel skip memory system of claim 1 wherein said connecting means comprises a diode having its anode connected to said manual-scan means and said clock means and its cathode connected to said squelch control.

7. Channel skip memory system of claim 1 wherein said counter means comprises a clock input connected to said clock means, the maximum count output of said plurality of outputs connected to a reset input of said counter and a clock enable input connected to ground whereby said counter when counting in numerical sequence automatically resets itself to cyclically scan said channels seriatim.

8. Channel skip memory system of claim 1 wherein said plurality of first logic means comprises an equal plurality of NAND logic gates.

9. Channel skip memory system of claim 1 wherein said plurality of memory means comprises an equal plurality of bistable multivibrators.

10. Channel skip memory system of claim 9 wherein each of said bistable multivibrators comprises two cross-coupled NAND logic gates for each of said plurality of multivibrators.

11. Channel skip memory system of claim 1 wherein said plurality of second logic means comprises an equal plurality of NAND logic gates.

12. Channel skip memory system of claim 1 further comprising a plurality of visual indicating means, each of said plurality of visual indicating means connecting to each of said plurality of second logic means to provide visual indication when each channel is scanned, manually or automatically.

13. Channel skip memory system of claim 12 wherein each of said visual indicating means comprises a light emitting diode.

14. Channel skip memory system of claim 1 wherein the combination of said plurality of first logic means and said plurality of memory means comprises an equal plurality of resettable memory elements.

15. Channel skip memory system of claim 14 wherein each of said resettable memory elements comprises a J-K flip-flop whereby said J-K flip-flop has inputs connected to said counter output, a clock input of said J-K flip-flop connects to said channel skipping means, a set input of said J-K flip-flop connects to said manual-scan means, and an output of said J-K flip-flop connects to said input of said second logic means.

16. Channel skip memory system of claim 14 wherein said reset means comprises a capacitor whereby said manual-scan means being switched from the scan position to the manual position thereby resetting said equal plurality of resets memory elements.

17. Channel skip memory system of claim 14 wherein said reset means comprises a capacitor whereby actuating said channel skipping means in the manual-mode once again for an inhibited channel subsequently enables that channel so that the channel will not be skipped.

18. Channel skip memory system of claim 14 wherein said reset means comprises a capacitor whereby actuating said channel skipping means can upon actuation inhibit channels received in the scan mode of operation, inhibit channels sequentially stepped to by said counter means in the manual-mode of operation and subsequently skipped when sequentially scanned in the scan mode of operation.

19. Channel skip memory system of claim 1 further comprises a plurality of status indication means connected to each of said plurality of memory means.

20. Channel skip memory system of claim 19 wherein said status indicating means comprises a light emitting diode for each of said plurality of memory means.

21. Channel skip memory system of claim 1 further comprising a plurality of status indication means connected to each of said plurality of memory means whereby said indication means indicates the enable and inhibit status of each channel.

22. Channel skip memory system of claim 1 wherein said channel skipping means comprises a momentary, normally open single pole single throw switch.

23. Channel skip memory system of claim 1 further comprising a channel stepping means and pulse means connected between said channel stepping means and said counter whereby said stepping means actuates said counter through said pulse means each time said stepping means is actuated to step and receive each channel seratimly.

24. Channel skip memory system of claim 23 wherein said channel skipping means comprises a momentary single pole double throw switch.

25. Channel skip memory system of claim 23 wherein said pulse means comprises a bistable multivibrator which acts as a noise suppressor for said channel stepping switch.

26. Channel scanning system of claim 23 wherein said pulse means comprises a cross-coupled NAND gate flip-flop.

27. Channel skip memory system of claim 1 wherein said channel skipping means comprises a short pulse generation means.

28. Channel skip memory system of claim 1 wherein said channel skipping means comprises a switch.

29. Channel skip memory system of claim 1 wherein said reset means comprises a capacitor whereby said manual-scan means being switched from the scan position to the manual position resets said memory means.