Driving pulse width controlling circuit for a transducer of an electronic timepiece

• US 4,114,364 A
• Filed: 01/28/1977
• Issued: 09/19/1978
• Est. Priority Date: 01/29/1976
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Daini Seikosha
• Original Assignee: Kabushiki Kaisha Daini Seikosha
• Inventors: Takahashi, Norio
• Primary Examiner(s): Jackmon, Edith S.
• Application Number:
  US05/763,714
• Time in Patent Office: 599 Days
• Field of Search: 58/23 AD, 58/23 BA, 58/23 D, 235/92 T, 235/92 EA, 235/156, 318/14, 318/317, 318/430, 318/432, 318/434, 318/127-129, 318/134, 318/139, 318/699, 315/169 TV
• US Class Current: 368/219
• CPC Class Codes: G04C 3/143 Means to reduce power consumption by reducing pulse width or amplitude and related problems, e.g. detection of unwanted or missing step
• CPC Class Codes: Y10S 388/93 Load or torque

Abstract

In an analogue electronic timepiece having a transducer comprising a rotor, a stator and a driving coil, means is provided for supplying to the driving coil, periodic pulses of a selected width to drive the rotor. The width of the pulses is automatically controlled according to the load of the transducer so as to reduce power consumption and accordingly to increase the useful life of the battery by which power is supplied.

Claims

1. In an analogue electronic timepiece, the combination of a transducer comprising a rotor, a stator and a driving coil, means including a power source for periodically supplying to said driving coil electric pulses of a selected width to drive the rotor and means for automatically controlling the pulse width according to the load of the transducer and thereby reduce power comsumption, said pulse supplying means comprising two transducer driving inverters of which the outputs are connected respectively to opposite terminals of said driving coil, means supplying a clock signal, a first flip-flop having Q, Q and CL terminals, a second flip-flop having Q, CL and R terminals, a first NAND circuit having output terminal connected with one of said transducer driving inverters and three inputs connected respectively with said clock signal supply means, the Q terminal of said second flip-flop and the Q terminal of said first flip-flop, and a second NAND circuit having an output connected to the other transducer driving inverter and three inputs connected respectively with said clock signal supply means, said Q terminal of said second flip-flop and the Q terminal of said first flip-flop.

2. A combination according to claim 1, in which said pulse width controlling means comprises means for sensing the current of said driving coil and means for terminating the driving pulse applied to said coil when said current reaches a predetermined value.

3. A combination according to claim 2, in which said current sensing means comprises an MOS transistor connected between said transducer driving inverters and a power source and means for terminating the driving pulse when the current of said transistor reaches a saturation value.

4. A combination according to claim 3, in which the saturation current value of said transistor is lower than the value of the voltage of the power source divided by the direct current resistance of the transducer driving coil.