Multiple bit deskew buffer

• US 4,115,759 A
• Filed: 08/08/1977
• Issued: 09/19/1978
• Est. Priority Date: 08/08/1977
• Status: Expired due to Term

• Current Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Original Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Inventors: Besenfelder, Edward Roald
• Primary Examiner(s): Atkinson, Charles E.
• Application Number:
  US05/822,476
• Time in Patent Office: 407 Days
• Field of Search: 340/146.1 F, 360/26, 364/900
• US Class Current: 714/700
• CPC Class Codes: G11B 20/20 for correction of skew for multitrack recording

Abstract

A multiple bit deskew buffer while providing skew correction for multi-track data read on mass storage devices is disclosed. All data transfers are synchronized to one basic clock eliminating the multiple clocking systems utilized in the prior art. The invention is arranged such that it could be easily modified so as to vary the number of bytes of data held in the byte buffer by either hardware, firmware, or software means.

Claims

1. In a data processing system which utilizes a plurality of apparatus for reading digital data from mass storage devices and a plurality of data and error detectors, a multiple bit deskew buffer comprising:

a plurality of bit tracking and storing sections, each of said sections comprising;

a position counter responsive to a one of said plurality of data and error detectors for determining the number of bits stored in the section;

a position decoder/overload detector responsive to the outputs of the position counter for providing individual error signals and a digital count of the number of bits stored in the section;

a control shift register responsive to said digital count and to the data and error detector for providing a bit ready output signal indicating that a bit of data from that section is now ready to be read;

a data shift register responsive to said digital count and to the data and error detector for providing a data output corresponding to the bit ready output signal of the control shift register;

the data shift register also providing means for storing a plurality of data bits;

an error register responsive to the data and error detector and to the error signals from the position decoder/overload detector for providing a track error signal when an error is detected, said track error signal forcing the bit ready output signal to indicate that a bit is ready to be read and forcing the data shift register data output to indicate that a logic "0" data bit is ready to be read;

a byte ready detector responsive to the bit ready output signal of each of said control shift registers and to the strobe output signal of each of the data and error detectors for providing an output signal indicating that one byte of data is properly aligned and ready to be transmitted, and

a byte buffer responsive to the output of the byte ready detector and the data output of each of said data shift registers for providing one byte of deskewed data as an output.

2. A multiple bit deskew buffer as recited in claim 1, wherein said position counters further comprise a multiple bit, up/down, binary counter with load and clear capabilities.

3. A multiple bit deskew buffer as recited in claim 1, wherein said position decoder/overload detector further comprises a binary to decimal decoder, the decimal (2) output being an error output when the system is operating in the write mode and the decimal (6) output being an error indicator when operating in the read mode.

4. A multiple bit deskew buffer as recited in claim 1, wherein said control shift register and said data shift register comprise a multiple bit, parallel in/parallel out, serial clocked shift register with load and clear capabilities;

the load function so configured as to allow the loading only of logical "1" inputs.

5. The multiple deskew buffer as recited in claim 1, wherein said error register further comprises means for detecting an error signal from either the data and error detector or the control shift register and providing a track error signal output when an error input signal occurs.

6. A multiple deskew buffer as recited in claim 1, wherein the byte ready detector further comprises;

a first multiple bit AND gate each of whose input is connected to a one of said plurality of control shift register bit ready output signals for providing a signal indicating that all bit tracking and storage sections are ready to transfer one bit of data to the byte buffer;

a second multiple input AND gate each of said inputs connected to a one of said plurality of data and error detector strobe output signals for providing a signal indicating that none of the bit tracking and storage sections is in the process of accepting a bit of data from the data an error detector; and

control means responsive to the outputs of the first and second AND gates for providing a byte read signal and a byte buffer ready signal.

7. The multiple bit deskew buffer as recited in claim 1, wherein the byte buffer further comprises:

a multiple bit parallel in/parallel out resettable register, said register connected to the data shift register data output signal of each of said sections and the byte buffer ready output of the byte ready detector for latching a deskewed byte of data for transfer; and

control means for providing a reset signal to the byte ready detector after the deskewed byte of data has been read from the register.

8. A multiple bit deskew buffer for use in a device for reading multi-track data from mass storage devices utilizing a data and error detector in each data track comprising:

a plurality of data positioning means for providing a bit ready signal and a data signal, each of said plurality of positioning means comprising;

counter means responsive to a corresponding one of the data and error detectors for providing an output signal indicative of the number of bits of data that has been read but not yet transferred from the positioning means;

decoding means connected to the counter means for providing a unique output for each state of said counter means and a plurality of error signals;

data storage means responsive to the data and error detector and the counter means for storing bits of data that have been read but not yet transferred from the position means;

control means responsive to the decoder means for providing an output signal corresponding to a one of the bits of data stored in the data storage means;

error recognition means connected to the corresponding data and error detector and the decoder means for providing an error signal that will force the output of the data storage means and the control means to a predetermined state;

byte detection means responsive to the output of each of said control means for providing an output signal indicating that each bit of the data byte is now deskewed and ready to be transferred; and

byte buffer means connected to the output of each of said data storage means for providing a multiple deskewed byte output.