Device for automatically loading the central memory of electronic processors

• US 4,117,974 A
• Filed: 12/23/1976
• Issued: 10/03/1978
• Est. Priority Date: 12/24/1975
• Status: Expired due to Term

• Current Assignee: CSELT Centro Studi e Laboratori Telecomunicazioni SpA (Telecom Italia S.p.A.)
• Original Assignee: CSELT Centro Studi e Laboratori Telecomunicazioni SpA (Telecom Italia S.p.A.)
• Inventors: Ciaramella, Alberto
• Primary Examiner(s): Atkinson, Charles E.
• Application Number:
  US05/753,780
• Time in Patent Office: 649 Days
• Field of Search: 235/153 AK, 235/304, 235/312, 364/200, 364/900
• US Class Current: 714/805
• CPC Class Codes: G06F 11/004 Error avoidance G06F11/07 and subgroups take precedence
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/0766 Error or fault reporting or storing
• CPC Class Codes: G06F 9/4403 Processor initialisation

Abstract

An electronic data processor includes a computing unit CPU carrying out a main program on the basis of data stored in a central memory MC and transferred to it from a mass memory MM under the control of an ancillary program or "bootstrap" prerecorded in an external unit UE. The latter comprises a read-only memory RP storing the ancillary program, another read-only memory RM containing a set of microinstructions sequentially read out under the control of an address counter CRM to carry out the word-by-word transfer of the ancillary program to the central memory MC, and various components LCM, LSA, CFD for checking the correct performance of these operations and halting the transfer in the event of a malfunction while emitting an alarm signal.

Claims

1. In an electronic data-processing system including a central memory, computing means for executing a main program on data stored in said central memory, and a mass memory containing data to be selectively introduced into said central memory preparatorily to the execution of said main program,

the combination therewith of an external unit, independent of said computing means, comprising:

storage means containing an ancillary program to control the selective introduction of data from said mass memory into said central memory;

operating means connected to said storage means for carrying out a transfer of at least a part of said ancillary program to said central memory in response to a starting command; and

check means connected to said operating means for verifying the correct performance of said transfer and halting said transfer upon detecting a malfunction.

2. The combination defined in claim 1 wherein said storage means includes a first read-only memory containing said ancillary program, and first counting means connected to said first memory for identifying a series of words of said ancillary program to be successively read out to said central memory;

said operating means including a second read-only memory containing a set of microinstructions, second counting means connected to said second memory for identifying the microinstructions to be successively read out therefrom, and logical circuitry connected to said second memory and to said check means for advancing said first and second counting means in response to said microinstructions and in the absence of a malfunction indication.

3. The combination defined in claim 2 wherein said check means comprises a parity-checking circuit connected in parallel with said logical circuitry to said second memory for verifying the correctness of each microinstruction read out therefrom.

4. The combination defined in claim 3 wherein said external unit includes timing means controlling the advance of said second counting means, said parity-checking circuit having an output connection to said timing means for arresting said second counting means upon detecting an incorrect microinstruction.

5. The combination defined in claim 4, further comprising alarm means connected to said second counting means for signaling an arrested condition thereof.

6. The combination defined in claim 2 wherein said check means comprises comparison means with inputs tied to said first memory and via a feedback connection to said central memory for verifying the identity of words read out from said first memory as part of said ancillary program with corresponding entries in said central memory.

7. The combination defined in claim 6 wherein said check means further comprises confirmation means communicating with said central memory for detecting the writing of said entries in said central memory and the readout thereof over said feedback connection.

8. The combination defined in claim 7 wherein said logical circuitry comprises a first and a second logic network with input connections to said second memory, said first logic network having an output connection to said confirmation means for activating same in response to certain microinstructions read out from said second memory, said second logic network having input connections to said comparison means and to said confirmation means and having an output connection to a stepping input to said second counting means for advancing the latter in the absence of an inhibiting signal on either of its said input connections.

9. The combination defined in claim 8 wherein said operating means further includes third counting means connected to said second memory for receiving therefrom the address of a location of said central memory in which a first word from said first memory is to be written, said third counting means having a stepping input connected to an output of said first logic network, said third counting means and said first memory being provided with enabling circuitry controlled by said first logic network.

10. The combination defined in claim 9 wherein said operating means further includes register means connected to said second memory for receiving therefrom the address of a final location of said central memory in which a word from said first memory is to be written, and a comparator with inputs tied to said register means and said first counting means for detecting the end of a transfer cycle, said comparator having an output connection to said second logic network.