Programmable question and answer device

• US 4,118,876 A
• Filed: 10/04/1976
• Issued: 10/10/1978
• Est. Priority Date: 10/04/1976
• Status: Expired due to Term

• Current Assignee: Antony A. Brilakis
• Original Assignee: Antony A. Brilakis
• Inventors: Brilakis, Antony A.
• Primary Examiner(s): Hum, Vance Y.
• Application Number:
  US05/729,591
• Time in Patent Office: 736 Days
• Field of Search: 35/6, 35/8 R, 35/9 R, 35/9 A, 35/9 B, 35/9 C, 35/9 D, 35/30, 35/31 C, 35/48 R, 35/8 A, 35/10, 35/8, 35/9, 35/31, 35/48, 364/200 MS File, 364/900 MS File
• US Class Current: 434/335
• CPC Class Codes: G09B 7/06 of the multiple-choice answer-type, i.e. where a given question is provided with a series of answers and a choice has to be made from the answers

Abstract

A programmable question and answer device having combined testing and teaching modes with multiple answer set programs. The device is comprised of a plurality of answer keys mounted on a housing, non-volatile, read only memory having a plurality of stored binary words parallelably outputted by a corresponding parallel input address code, control logic connected to the read only memory, program selector, and display. The program selector includes an activator strip having a coded pattern corresponding to a selected answer set. When the activator strip is inserted into the device, a particular program sequence is initiated. The display includes a display showing the accumulated score of correctly answered questions, next question number display, correct answer display when an incorrect answer key is depressed, and indicators to show when a question has been correctly or incorrectly answered. Due to the large number of different answer sets available from the read only memory and program selector, a student cannot memorize the answer sequences during repeated testing.

Claims

1. A programmable question and answer device having combined testing and teaching modes with multiple answer set programs, said device comprising in combination:

a housing;

a plurality of indexed answer keys mounted on said housing;

control logic means connected to said answer keys, said control logic means having parallel address means;

non-volatile read out memory means electrically connected to said control logic means, said memory means having a plurality of stored binary words output in parallel by said parallel address means;

program selector means selectively connected to said read only memory means, said control logic means and said answer keys in order to program an operational sequence for a selected answer set; and

,

a plurality of electrically activated display means selectively connected to said control logic means for indicating question and answer data;

said control logic means comprises, sequencing logic means connected to said display means and said read only memory means for advancing binary data during an answer program sequence, comparison logic means connected to said program selector means to check validity of permissible answers and student answers in each answer set and display timing means connected to said comparison logic means and said display means to limit viewing time of displays showing correctness of a student'"'"'s answer;

said sequencing logic means comprises, a first binary counter connected to said display means for accumulating the number of correctly answered questions for each answer set, a second binary counter connected to said display means to indicate the number of the next question within an answer set, and a third binary counter connected by parallel lines to said read only memory means for addressing said read only means in order to output a selected binary word.

2. A device as claimed in claim 1, wherein said comparison logic means is comprised of:

a first digital comparator connected to said program selector means to determine if an outputted answer from said read only means is zero or greater than a selected number; and

a second digital comparator connected to said program selector means and said display timing means to determine the correctness of a student'"'"'s answer.

3. A device as claimed in claim 2, wherein said program selector means is comprised of:

a plurality of springlike electromechanical switches mounted in said housing and electrically connected to said read only memory, said first digital comparator, and said second digital comparator; and

an electrically insulative activator strip having a conductive printed circuit coded pattern corresponding to a selected answer set, said activator strip insertably mounted in said housing and selectively engaging said electromechanical switches so that a particular program sequence is effected corresponding to a selected answer set.

4. A device as claimed in claim 2, wherein said program selector is comprised of:

a first array of electrically conductive metallic pads formed into a grid pattern and mounted on a plane surface on said housing, said metallic pads selectively connected to said read only memory, said first digital comparator, and said second digital comparator;

a hinged cover element mounted on said housing and in alignment with said first array of metallic pads, said cover element having its lower surface covered with a second array of electrically conductive elastomer pads formed into a grid pattern; and

an insulative activator strip insertably mounted between said first array of metallic pads and said second array of elastomer pads, said activator strip having coded slots in alignment with said first and second array of pads so that a particular program sequence is produced corresponding to a selected answer set when said first array of metallic pads are selectively switched by contacting said cover element elastomer pads, under pressure, through said coded slots of said activator strip.

5. A device as claimed in claim 2, wherein said display means is comprised of:

a first display means connected to said sequencing logic means indicating the accumulated score of correctly answered questions;

a second display means connected to said display sequencing logic indicating the number of the next question to be answered;

a third display means connected to said display timing means indicating when a question has been correctly answered;

a fourth display means connected to said display timing means indicating when a question has been incorrectly answered; and

a fifth display means connected to said first digital comparator indicating the correct answer when an incorrect answer key was depressed.

6. A device as claimed in claim 1, wherein said display timing means is comprised of:

a first electronic timer connected to said comparison logic means, said first electronic timer energized for a predetermined time whenever a student makes a correct answer; and

a second electronic timer connected to said comparison logic means, said second electronic timer energized for a predetermined time whenever a student makes an incorrect answer.