Bingo computer apparatus and method

• US 4,121,830 A
• Filed: 08/29/1977
• Issued: 10/24/1978
• Est. Priority Date: 08/29/1977
• Status: Expired due to Term

• Current Assignee: Random Electronic Games Company
• Original Assignee: Random Electronic Games Company
• Inventors: Buckley, Dennis J.
• Primary Examiner(s): Hum, Vance Y.
• Application Number:
  US05/828,645
• Time in Patent Office: 421 Days
• Field of Search: 273/1 E, 273/138 A, 273/237, 273/139, 328/59, 331/78, 340/323 R, 364/717
• US Class Current: 463/22
• CPC Class Codes: G07C 15/006 electronically

Abstract

A bingo computer in which every number has a storage location in an addressable memory and a "pick" counter sequentially addresses the memory at a high rate of speed for locations picked and a much lower rate for locations not picked. A display counter shares the memory.

Claims

1. A random number selector for games comprising:

(a) a memory having an addressable storage location for each number in a game;

(b) means to sequentially address each said storage location;

(c) random selection means to selectively record a pick at a storage location when it is addressed and including means for picking a number;

(d) first clock means operating at a first cyclical rate for clocking said means to sequentially address through each said storage location;

(e) gate means for blocking said clocking;

(f) second clock means operating at a second cyclical rate connected to enable said gate means at the beginning of each cycle of said second cyclical rate;

(g) disabling means connected from said memory for disabling said gate after each unpicked number location in said memory has been addressed, the frequency of said first cyclical rate being greater than the frequency of said second cyclical rate by at least the number of said addressable storage locations whereby unpicked number locations are addressed consistently at said second cyclical rate irrespective of the sequential addressing of already picked number locations.

2. A random number selector according to claim 1 wherein said means to sequentially address is a first counter, a second counter is connected to sequentially and simultaneously address both said storage locations and a numerical display and a multiplexer is connected between said memory and both said first and said second counter, said multiplexer being operative to apply the address from said first counter to said memory for one half of each period of said first clock means and operative to apply the address from said second counter to said memory for the other half of each period of said first clock means.

3. A random number selector according to claim 2 including a last number picked display and a latch circuit wherein said first counter addresses said last number picked display simultaneously with addressing said memory and said latch circuit, said latch circuit being connected between said first counter and said last number picked display for latching only addresses of numbers just picked and holds them until a new number is picked.

4. A random number selector according to claim 1 further comprising a clock generator and a scaler which is connected to said generator for providing said first clock means and said second clock means.

5. A random number selector according to claim 1 wherein said memory is a digital random access memory.

6. A random number selector according to claim 1 wherein said gate means for blocking said clocking comprises an AND gate, a flip-flop having set and reset inputs, a connection from said second clock means to the SET input of said flip-flop, reset means connected to the reset input of said flip-flop and responsive to a simultaneous output from said AND gate and an unpicked address output from said memory to reset said flip-flop, a connection from an output of said flip-flop to an input of said AND gate to enable said AND gate when said flip-flop is set, and a connection from said first clock means to a second input of said AND gate whereby said AND gate passes pulses from said first clock means to said counter when said flip-flop is set, and said flip-flop is reset, blocking said pulses, when a pulse passing said AND gate coincides with the addressing of an unpicked location in said memory.

7. A random number selector according to claim 1 including a manual pick switch wherein the frequency in Hertz of said second clock means is greater than the number of said storage locations whereby it is impossible for a human being to operate said manual PICK switch so as to affect the likelihood of certain numbers being picked.

8. A method of sequencing selections through a fixed number of digital storage locations in which picked selections are deleted from further selection without loss of randomness comprising:

(a) addressing said digital storage locations by a counter;

(b) sequencing said counter at a first clock rate when the locations addressed have not been previously selected;

(c) sequencing said counter at a second clock rate faster than said first clock rate by enough to address every location of said digital storage locations during a single cycle at said first clock rate when the location addressed have been previously selected; and

,

(d) inhibiting selection when said counter addresses locations previously selected.