Video processor for distance measuring equipment

• US 4,124,850 A
• Filed: 06/07/1977
• Issued: 11/07/1978
• Est. Priority Date: 06/07/1977
• Status: Expired due to Term

• Current Assignee: The Bendix Corporation (Honeywell International Inc.)
• Original Assignee: The Bendix Corporation (Honeywell International Inc.)
• Inventors: Frazier, Richard V. Jr., Levenson, Tony
• Primary Examiner(s): Buczinski, S. C.
• Application Number:
  US05/804,415
• Time in Patent Office: 518 Days
• Field of Search: 343/6.5 LC, 343/7.3, 343/5 DP
• US Class Current: 342/48
• CPC Class Codes: G01S 13/16 using counters
• CPC Class Codes: G01S 13/787 co-operating with direction defining beacons

Abstract

A video processor for Distance Measuring Equipment in which all timing functions including fixed delays are performed by digital counters counting clock pulses from a highly stable source. Search and track operations are conducted by starting a memory counter by a reply from a responser and stopping the memory counter at a time corresponding to maximum range. On a succeeding interrogation cycle the memory counter is started prior to the time a reply at zero range would be received. In this cycle the memory counter begins count with the count it contained when stopped during the previous cycle; the memory counter counts until it reaches a number corresponding to maximum range, stops and initiates a range gate. A reply within the range gate causes the range gate to be repeated at the same time in the following interrogation cycle. A sufficient number of replies within the range gate cause tracking operation to begin. A velocity memory provides continuing tracking during temporary loss of reply signals.

Claims

1. In a video processor for Distance Measuring Equipment, said Distance Measuring Equipment including means for transmitting interrogation signals to a responser station and means for receiving reply signals from said responser station, means for positioning a range gate to enable distance tracking of said reply signals comprising,

a source of clock pulses,

a memory counter for counting said clock pulses, said memory counter having a count capacity equal to the number of clock pulses which would occur during the time required for a signal to travel round trip between a Distance Measuring Equipment and a responser at maximum range of the Equipment,

means actuated by a reply from the responser for starting count by said memory counter during a first interrogation-reply cycle of the Equipment;

means for stopping count by said memory counter during said first interrogation-reply cycle at a time when a reply would have been received at maximum range between the Equipment and the responser;

means for restarting count by said memory counter during a second interrogation-reply cycle of the Equipment, said restarting means being actuated at a time prior to the time a reply would be received by the Equipment if located at zero range between the Equipment and the responser;

means for stopping and resetting said memory counter upon said memory counter'"'"'s reaching its full count capacity;

means actuated by said memory counter'"'"'s reaching full count for generating a fixed time period constituting a range gate; and

means for starting count by said memory counter a second time during said second interrogation-reply cycle whenever the reply is within said range gate.

2. A device as claimed in claim 1, with additionally,

means for determining whether the reply of an interrogation-reply cycle subsequent to said first interrogation-reply cycle occurs early or late in said range gate, and

means for adjusting said restarting means to cause restart of said memory during an interrogation-reply cycle subsequent to said first interrogation-reply cycle at a time earlier or later than restart occurred during said second interrogation-reply cycle according to whether said reply was determined to be early or late.

3. A device as claimed in claim 1 wherein said last-named means further provides for starting said memory counter a second time during said second interrogation-reply cycle whenever the reply is not within said range gate but occurs after the expiration of said range gate.

4. A device as claimed in claim 1 wherein said means for stopping count by said memory counter at a time when a reply would have been received at maximum range includes

a range counter for counting said clock pulses, said range counter having a count capacity equal to the count capacity of said memory counter;

means for starting count by said range counter at the time a reply would be received by the Equipment if located at zero range between the Equipment and the responser; and

means for stopping count by said memory counter whenever said range counter reaches its full count capacity.

5. A device as claimed in claim 1 wherein said means for generating a fixed time delay constituting a range gate comprises a range gate counter for counting said clock pulses, said range gate counter having a fixed count capacity and beginning count at zero when actuated by full count of said memory counter and continuing count until the full capacity of said range gate counter is reached, said fixed time period constituting said range gate being the time interval during which said range gate counter continues count.

6. A device as claimed in claim 5 wherein said means for restarting count by said memory counter includes:

means providing a first shift pulse whenever a reply occurs during count by said range counter through numbers less than the midvalue of the count capacity of said range counter;

means providing a second shift pulse whenever a reply occurs during count by said range counter through numbers greater than the midvalue of the count capacity of said range counter; and

a shift register having a digital bit preset therein and shifting said bit toward one output terminal thereof by said first shift pulse and shifting said bit toward another output terminal by said second shift pulse, said bit when shifted to said one or another output terminal determining the time of restarting count by said memory counter in an interrogation reply cycle succeeding said second interrogation-reply cycle.

7. A device as claimed in claim 6 wherein said bit is preset in said register so as to require a different number of said first shift pulses to shift said bit to said one output terminal than the number of said second shift pulses required to shift said bit to said another output terminal.

8. A device as claimed in claim 6 with additionally

means for determining the frequency at which bits are shifted from said register and for providing output pulses at a frequency proportional to said determined frequency, and

means operable during temporary loss of reply signals for supplying output pulses from said frequency determining means to said restarting means in substitution for output pulses from said shift register.

9. A video processor for use in Distance Measuring Equipment to determine the time elapsing between initiation of an interrogation signal and the receipt and decoding of a reply signal, comprising,

a source of clock pulses;

a first digital counter for accumulating said clock pulses and for generating at predetermined counts thereof;

(a) an interrogation pulse pair signal;

(b) a suppression pulse signal; and

(c) a first end of count signal;

a second digital counter enabled by said first end of count signal for accumulating a predetermined adjustable count of clock pulses and providing a second end of count signal;

a third digital counter enabled by said second end of count signal for accumulating a predetermined count of said clock signals and providing

(a) a relatively low selectable-count signal, and

(b) a relatively high fixed-count signal;

said relatively high fixed-count signal constituting a first reference pulse;

a fourth digital counter enabled by said first reference pulse for accumulating a count of said clock pulses corresponding to the maximum range at which the Distance Measuring Equipment is to be operated and providing a third end of count signal upon reaching said count corresponding to maximum range;

means including a fifth digital counter for determining the spacing between pulse signals received by the Distance Measuring Equipment to establish reception of a pair of pulse signals having a predetermined spacing and for generating a delayed reply signal after a pair of pulses of said predetermined spacing has been received and after said fifth digital counter has counted a fixed number of said clock pulses beginning such count with the reception of the first pulse of said pair of predetermined spacing;

distance tracking means including sixth and seventh digital counters, said sixth counter constituting a memory counter, said seventh counter constituting a range gate counter,

during a first interrogation cycle consisting of the transmission and reception by the Distance Measuring Equipment of an interrogation pulse pair and a reply pulse pair, said memory counter beginning count of said clock pulses upon the appearance of said delayed reply signal and ending count upon the appearance of said third end of count signal,

during a succeeding interrogation cycle said memory counter beginning count upon the appearance of said selectable count signal from said third counter and providing a fourth end of count signal upon reaching a count equal to the maximum range count of said fourth counter,

said range gate counter beginning count of said clock pulses upon the appearance of said fourth end of count signal and providing a range gate center signal constituting a second reference pulse upon reaching a count intermediate of the counting capacity of said range gate counter, and

means for restarting the count of said clock pulses by said memory counter during that same succeeding interrogation cycle either

(a) upon the appearance of said range gate center signal, or

(b) upon the appearance the first said delayed reply signal to occur after said range gate counter reaches its full count capacity.

10. A video processor as claimed in claim 9 wherein said last named means includes,

means for determining whether said delayed reply signal occurs during the interval when said range gate counter is actively counting.

11. A video processor as claimed in claim 9 with additionally

means providing an early signal whenever said delayed reply signal appears during the interval when said range gate counter is actively counting and before said range gate center signal is produced,

means providing a late signal whenever said delayed reply signal appears during the interval when said range gate counter is actively counting and after said range gate center signal is produced, and

means controlled by said early signals and said late signals for selecting the count of said third digital counter means at which said memory counter is started.

12. A video processor as claimed in claim 11 wherein said last named means includes a digital shift register having a digital bit preset therein, said early signal and said late signal respectively shifting said bit toward one and toward another output terminal of said register, the appearance of said bit at said one or said another output terminal of said register determining said count selected from said third digital counter means.

13. A video processor as claimed in claim 12 with additionally

means for determining the frequency at which bits appear at said one or another terminal of said register and for providing a memory signal having a frequency proportional to said determined frequency, and

means utilizing said memory signal for determining said count selected from said third digital counter during temporary loss of reply signals.

14. A video processor as claimed in claim 13 wherein said last named means includes

an eighth digital counter for counting as an event the appearance of said delayed reply signal during the interval when said range gate counter is actively counting, and

a ninth digital counter for counting as an event the absence of said delayed reply signal during the interval when said range gate counter is actively counting,

said ninth counter having a greater count capacity than said eighth counter, both said eighth and ninth counters being reset upon either said eighth or ninth counter reaching full count, said full count of said ninth counter causing said memory signal to be utilized for determining said count selected from said third digital counter.

15. A video processor as claimed in claim 14, with additionally

means responsive to the length of time in which full counts by said eighth counter occur for limiting the length of time during which said memory signal is utilized for determining said count selected from said third digital counter.