Peripheral-unit controller apparatus
First Claim
1. In a peripheral-unit controller adapted to interconnect a peripheral unit and a digital computer unit for the control of data signals being transferred therebetween, a control device comprising:
- a plurality of read-only memory units, each such unit having a plurality of input lines and a corresponding plurality of output lines;
each of said memory units having a set of microcode words stored therein, any word of which may be applied to said plurality of output lines of said memory units in accordance with address signals applied to said plurality of input lines of said units, the sets of microcode words stored in the respective memory units being different from each other;
means for applying a set-selection signal to at least one of said plurality of input lines for selecting only one of said sets of microcode; and
means for applying a plurality of address signals to others of said input lines for transferring a particular microcode word of said selected set of said microcode words to said plurality of output lines to control said peripheral unit.
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Accused Products
Abstract
A distributed input/output system is disclosed for controlling numerous peripheral devices and the transfer of data signals and control signals between those devices and a general purpose digital computer. The control system described includes a multiplexer which can accommodate as many as eight input/output devices under the control of separate programmable microcoded peripheral-unit controllers. Each controller is adapted to be located at or on an individual peripheral device and each is connected to the multiplexer by an identical ribbon cable that is employed to carry both signals and power. Each controller employs a substantially identical microengine, that is, a microcoded processor, currently of five integrated circuit chips. The peripheral-unit controllers may be configured somewhat differently depending upon whether the peripheral device utilizes data signals in parallel or in series. Data may be transferred directly between a computer memory unit and the peripheral devices without requiring the use of any computer working registers and without requiring subroutines to preserve an ongoing main program. Each peripheral-device controller can issue interrupt signals which are processed by the computer on a priority basis when they occur simultaneously. Some microengines employ two sets of programmed microcodes and each set is selectable by a switch, such as a wire jumper, for controlling either of two different kinds of devices.
61 Citations
26 Claims
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1. In a peripheral-unit controller adapted to interconnect a peripheral unit and a digital computer unit for the control of data signals being transferred therebetween, a control device comprising:
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a plurality of read-only memory units, each such unit having a plurality of input lines and a corresponding plurality of output lines; each of said memory units having a set of microcode words stored therein, any word of which may be applied to said plurality of output lines of said memory units in accordance with address signals applied to said plurality of input lines of said units, the sets of microcode words stored in the respective memory units being different from each other; means for applying a set-selection signal to at least one of said plurality of input lines for selecting only one of said sets of microcode; and means for applying a plurality of address signals to others of said input lines for transferring a particular microcode word of said selected set of said microcode words to said plurality of output lines to control said peripheral unit.
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2. In a peripheral unit controller dedicated to interconnecting a computer and a peripheral device of a specific type, for the management of data signals and coded control signals transmitted between said computer and said peripheral device, each said coded control signal corresponding to a different predetermined sequence of operations of said peripheral device, said peripheral unit controller being located proximate to said peripheral device, the improvement wherein said controller comprises:
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control means for receiving such coded control signals and data signals from said computer and storing data signals from said computer, said control means comprising processing means for processing such control signals received by said control means from said computer, each said coded control signal corresponding to a particular microcode word, said processing means comprising; memory means for storing a plurality of such microcode words, each microcode word comprising a plurality of microcode signals; means directly responsive to each of said received coded control signals respectively and for reproducing a series of said stored microcode words in a selected predetermined sequence; and means responsive to at least one of said reproduced stored microcode words from said series for sequencing said peripheral device through a corresponding predetermined series of operations; and means controlled by one of such microcode words in said reproduced series for also transmitting said data signals to said peripheral device after sufficient time has elapsed for said sequence of operations to be completed.
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3. In a controller adapted to interconnect a digital computer unit and a peripheral unit and to manage the transfer of data signals from one of the units to the other, the improvement wherein said controller comprises:
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a memory unit having a program stored therein, said program including a plurality of control words, each such word having a plurality of control signals; a data selector unit having a plurality of input lines for transferring respective data signals into said data selector unit, having a single output line for transfer of a selected one of said data signals out of said data selector unit, having a plurality of data selection lines for transfer of data selection signals from said memory unit to said data selector unit, and having means for selecting one of said data signals in accordance with said selection signals for transfer of said selected one data signal out of said data selector unit as an output signal, some of said data signals being logically TRUE in a positive voltage state and others being logically TRUE in a negative voltage state; memory addressing and selecting means including a counter unit having count select lines for transfer of at least two count select signals to said counter unit, one of which is coupled to said memory unit for receiving input control signals from said memory unit and the other of which is coupled to receive signals from said data selector unit, said memory addressing and selecting means having means responsive to said input control signals applied to said count select lines to establish a subsequent count in said counter for selecting a subsequent memory unit output control word in accordance with address signals corresponding to the count of said counter unit, said memory addressing and selecting means having output lines for transfer of said address signals from said counter unit to said memory unit, which address signals determine which control word is generated in the output of said memory unit, said counter unit including means for determining in accordance with said count select signals whether said input control signals are loaded into said counter unit to register a subsequent, original count or instead whether an increment operation is performed in said counter to generate and register a count that is an increment of a previously registered count, one of said count select lines being connected to receive a control signal generated by said memory unit and constituting a first count select signal and a second of said count select lines being connected to receive a signal corresponding to said output signal of said data selector unit and constituting a second count select signal; and a selectable inverter having means including an output line and at least two input lines, said output line being connected to said counter unit for transfer of said second count select signal from said selectable inverter to said counter, one of said input lines being connected to said output line of said data selector unit and another of said input lines being connected to said memory unit for transfer of an inverting signal from said memory unit to said inverter, the truth value of said inverting signal being determined by said memory unit and being selectively changed thereby, in accordance with said stored program to render constant the voltage states of said second count signal that corresponds to TRUE and FALSE truth values respectively, regardless of which voltage state of an output signal of said data selector unit corresponds to a TRUE truth value. - View Dependent Claims (4)
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5. In a peripheral-unit controller having first and second signal ports, said controller being for interconnecting a peripheral unit and a digital computer for the control of data signals being transferred therebetween through said ports,
a control unit adapted to control a sequence of data signal transfer operations through said ports in accordance with control signals generated by said computer; - a control device comprising;
a read-only memory unit having input lines and output lines and having a plurality of microcode words stored therein, any one of which may be applied to the output lines of said memory unit in accordance with a respective address signal applied to said input lines; means for applying any one of at least two sets of address signals to said input lines, one such set being transferable thereto from said output lines and the other set being transferable thereto from said computer unit; means responsive to a select signal including a component of each microcode word supplied by said output lines for selecting one or the other of said two sets of address signals to be next transferred to said input lines; and means responsive to the transferred set of address signals for generating on said output lines said one such set of address signals, such a component, and control signals for applying data signals received from said digital computer through said first port to said peripheral unit through said second port. - View Dependent Claims (6)
- a control device comprising;
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7. Apparatus for interconnecting a digital computer unit and a peripheral unit comprising
A. a controller separate from said computer unit and from said peripheral unit and adapted, when connected to said units, to receive count, that is external address, signals from one of said units, and to manage the transfer of data signals from one of said units to the other; -
B. first cable connect means in said controller and serving as a first port for operatively connecting said controller to said digital computer unit for transferring signals therebetween, and second cable connect means in said controller and serving as a second port for operatively connecting said controller to said peripheral unit for transferring signals therebetween; C. microengine means in said controller, said microengine means comprising (1) a multiplexer having first and second sets of address input terminals and a set of address output terminals, (2) means for applying such external address signals received through said first port to said first set of multiplexer input terminals; (3) a controller memory means having a plurality of count input terminals and also having a plurality of output lines, (4) said memory means including means responsive to each of a plurality of count signals applied to said count input terminals and for generating a corresponding set of program word signals on said output lines, each said set of program word signals being different according to the count applied to said count input terminals, each said program word signal comprising an enable signal, an internal branch address signal, and a control signal; D. a program counter in said controller having a set of count input terminals connected to the address output terminals of said multiplexer and having a set of count output terminals connected to said count input terminals of said memory means, said counter comprising count register means associated with said count output terminals, said counter also having enable signal input means selectively responsive to a count enable signal pattern for selectively storing in said register means the count applied to said count input terminals or else for incrementally altering the count currently stored therein and storing the incremented count therein; E. one subset of said output lines of said controller memory unit manifesting said internal branch address signal and being connected to said second address input terminals of said multiplexer; F. another subset of said output lines of said controller memory unit manifesting a control signal; G. an enable output line of said controller memory unit manifesting an increment enable signal and connected to the count enable input means of said program counter to form part of such count enable signal pattern; and H. signal means for intermittently rendering said microengine means operative to apply a count from said register means to said memory means. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. In a controller having two ports and adapted to receive data signals through one of said ports and to transmit such signals out of the other, the improvement comprising:
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a control means in said controller, said control means including at least one memory unit having means for storing program instruction words therein, said instruction words being composed of bits, and having a subset of output lines on which a set of output bit signals is manifested in accordance with a selected program word, each said bit signal having a truth value, and including a program counter connected to said memory unit and including a register to supply an address count signal to said memory unit to select a corresponding program word whereby the truth values of the output signals manifested on a subset of said output lines of said memory unit at any one time is determined by the address count signal supplied thereto by said counter, count signals sometimes representing an original program count and count signals sometimes representing an altered program count that is incrementally related to a previously manifested count, said counter having input lines, and including multiplexer means having output lines connected to said counter input lines and having first and second sets of input lines, one set of said input lines being connected to receive original address count signals through one of said ports, the other set of input lines being directly connected to said subset of memory unit output lines to receive original count signals from said subset of said memory unit output lines, said multiplexer including means directly controlled by one of said output bit signals to apply count signals from a selected one of such sets of input lines to the output of said multiplexer and thence to the input lines of said counter; and including program step control means selectively responsive to a program control signal including another output bit signal received directly from the output of said memory unit to alter the current count and to apply the altered count to said memory unit input lines when the program control signal has one value and to transfer an original count signal from said multiplexer input lines to said counter when the program control signal has another value, to establish a new address count signal in said register. - View Dependent Claims (15)
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16. In apparatus for interconnecting a digital computer unit and a peripheral unit:
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A. a controller separate from said computer unit and said peripheral unit being operative to receive count, that is external address, signals from said computer unit, and to manage the transfer of data signals from one of said units to the other; B. first cable connect means in said controller and serving as a first port for connecting said controller to said digital computer unit for transferring signals therebetween, and second cable connect means in said controller and serving as a second port for connecting said controller to said peripheral unit for transferring signals therebetween; C. microengine means in said controller, said microengine means comprising (1) a multiplexer having first and second sets of address input terminals and a set of address output terminals, (2) means for applying external address signals received through said first port to said first set of multiplexer input terminals; (3) a controller memory means having a plurality of count input terminals and also having a plurality of output lines and including means responsive to the value of each of a plurality of count signals applied to said count input terminals for generating a corresponding set of word program signals on said output lines, each said program signal being different according to the count applied to said count input terminals, each said word program signal comprising an enable signal, an internal branch address signal, a data select signal, a control signal, and a select address signal, said output lines being arranged and connected as set forth below; D. data selector means having a set of data input lines for receiving a plurality of data signals from one or another of said units and having a data output line, and having a set of selection terminals connected to select which of said data lines shall be operative to provide a data output signal to said data output line; E. a program counter having a set of count input terminals connected to the address output terminals of said multiplexer and having a set of count output terminals connected to the input terminals of said memory unit, said counter comprising count register means associated with said count output terminals, said counter also having enable signal input means selectively responsive to a count enable signal state for selectively storing in said register means the count applied to said count input terminals or for incrementally altering the count currently stored therein; F. an exclusive OR gate having two input terminals and a gate output terminal, one of said latter input terminals being connected to said data output terminal; G. said output lines of said controller memory means comprising (1) one subset of output lines being directly connected to said second address input terminals of said multiplexer and operative to carry such internal branch address signal to said second address input terminals, (2) a second subset of said output lines being directly connected to the selection terminals of said data selector and being operative to carry data select signals to said selection terminals, (3) a third subset of said output lines being operatively connected to carry control signals for managing the transfer of signals between said units; (4) a fourth subset comprising at least one output line carrying a select address signal connected directly to said multiplexer to select which set of input address signals shall be applied to the set of output terminals of said multiplexer, (5) a fifth output line carrying an increment enable signal and being operatively connected to the count enable input means of said program counter to enable alteration of the stored count; (6) a sixth output line carrying an invert signal, connected to the other input terminal of said gate for selectively inverting the data signal or not according to the value of said invert signal; H. means connecting said data output line to said counter enable means; I. means for applying said control signals to one of said cable connect means; and J. clock means for intermittently rendering said microengine means operative to apply to said memory unit the count stored in said register means and then to store a new count in said register means according to the values of said select address signal and said increment enable signal.
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17. In a controller having two ports and adapted to receive signals through one of said ports and transmit signals out of the other, said controller comprising;
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memory means for storing a plurality of microcode instruction signals, each microcode instruction signal comprising a plurality of microcode signals, including first and second address select signals, and an internal address signal, said memory means having means for generating a selected microcode instruction signal at the output of said memory means in accordance with a selection address signal applied thereto; address-select means having first and second inputs and having an output; means for receiving external branch address signals through said first port and for applying said signals to said first input of said address-select means; means for applying said internal address signal as an internal branch address to said second input of said address-select means; means for receiving a sequence of successive activating pulses; register means for registering a count, or address, signal; a status signal supply means for supplying a status signal; means in said address-select means directly connected to receive said first and second address-select signals and reponsive to said status signal and to the next successive activating pulse to selectively perform one of two operations, one operation involving applying to said register means one of said address signals, the other operation involving incrementing said applied selection address signal and applying said incremented signal count to said register means; and means for applying the registered count, or address, signal to said memory means as a selection-address signal to generate a corresponding microcode instruction signal each time the next activating pulse is received. - View Dependent Claims (18, 19, 20, 21)
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22. In a computer control unit for transfer of data signals from one component of a computer system to another component thereof, the improvement comprising:
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memory means for storing a plurality of microcode words, each microcode word comprising a plurality of microcode signals, including first and second and third select signals, an inverting signal, and an internal address signal, said memory means having means for generating a selected microcode instruction signal at the output of said memory means in accordance with a selection address signal applied thereto; address-select means having first and second inputs and having an output; means for receiving external branch address signals from one such component and for applying said signals to said first input of said address-select means; means for applying said internal address signals as an internal branch address to said second input of said address-select means without buffering; a status signal selector having input means for receiving a plurality of status signals for selecting any one of a plurality of status signals generated by said computer system, one set of said status signals having one voltage value when in a TRUE state and another set of said status signals having a low voltage value in a FALSE state; means controlled by said third select signal to select a predetermined corresponding one of said status signals; and means comprising an inverter and controlled by said inverting signal for inverting the selected status signal only if it is in one of said sets but not in the other whereby the voltages corresponding to the truth states of said status signals are standardized; means for receiving a sequence of successive activating pulses; register means for registering a count, or address, signal; means in said address-select means jointly responsive to said first and second address-select signals and to said selected status signal and to an activating pulse to selectively apply to said register means one of said address signals sometimes or alternatively, to increment said applied selection address signal and to apply to said register means said incremented signal at other times; and means for applying the registered count, or address, signal to said memory means as a selection-address signal to generate a corresponding microcode instruction signal.
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23. In a computer control unit for transfer of data signals from one component of a computer system to another component thereof, the improvement comprising:
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memory means for storing a plurality of microcode words, each microcode word comprising a plurality of microcode signals, including first and third select signals, internal address signals, an increment-enable signal, and control signals; means for generating a selected microcode word at the output of said memory means in accordance with a selection address signal applied thereto; address-select means having first and second inputs and having an output; means for receiving external branch address signals from one such component and for applying said signals to said first input of said address-select means; means for applying said internal address signals as an internal branch address to said second input of said address-select means; means for receiving a sequence of activating pulses; register means for registering a count, or address, signal; a status signal supply means for supplying a status signal; means in said address-select means jointly responsive to said first and second address-select signals without buffering and to said status signal and to the next successive pulse received to selectively apply to said register means one of said address signals or alternatively, to increment said applied selection address signal and to apply to said register means said incremented signal to provide a registered count, or address, signal; means for applying said registered address signal to said memory means as a selection-address signal to generate a corresponding microcode instruction signal; and means responsive to said control microcode signal to control one of said components.
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24. In a controller having first and second signal ports, said controller being adapted to interconnect a peripheral unit and a digital computer for the control of data signals being transferred therebetween through said ports, a control unit adapted to control a sequence of data signal transfer operations in accordance with control signals generated by said computer, said control unit comprising:
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a read-only memory unit for storing a plurality of microcode words therein and having input lines and output lines, any of which words may be applied to said output lines in accordance with respective address signals applied to input lines of said memory unit and each of said words including a select signal; means for applying any one of at least two sets of address signals to said input lines, one such set being transferred from said output lines and the other being received through one of said ports; means directly responsive to a select signal on one of said output lines for selecting one of said two sets of address signals to be next applied to said input lines; and means for applying the selected set of address signals to said input lines of said memory unit for generating on said output lines said one such set of address signals, and further control signals for controlling said peripheral unit.
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25. In a controller having two ports and adapted to receive signals through one of said ports and to transmit signals out of the other port:
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A. microengine means in said controller, said microengine means comprising (1) a multiplexer having first and second sets of address input terminals and a set of address output terminals, (2) means for applying address signals received through said first port to said first set of multiplexer input terminals; (3) a controller memory means having a plurality of count input terminals and also having a plurality of output lines and including means responsive to each of a plurality of count signals applied to said count input terminals for generating a corresponding set of program word signals on said output lines, each said set of program word signals being different according to the count applied to said count input terminals, each said program word signal comprising an enable signal, a branch address signal, and a control signal; B. a program counter having a set of count input terminals connected to the address output terminals of said multiplexer and having a set of count output terminals connected to the input terminals of said memory unit, said counter comprising count register, means associated with said count output terminals, said counter also having enable signal input means selectively responsive to a count enable signal pattern for storing in said register means the count applied to said count input terminals or else for incrementally altering and storing therein the count previously stored therein; C. one subset of said output lines of said controller memory unit manifesting an internal branch address signal and being directly connected to said second address input terminals of said multiplexer; D. an enable output line of said controller memory unit manifesting an increment enable signal and connected without buffering, to the count enable input means of said program counter to contribute to such signal pattern; E. means for transmitting said control signals to one of said cable connect means; and F. signal means for intermittently rendering said microengine means operative to apply a count from said register means to said memory means. - View Dependent Claims (26)
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Specification