Programmable array logic circuit

• US 4,124,899 A
• Filed: 05/23/1977
• Issued: 11/07/1978
• Est. Priority Date: 05/23/1977
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Monolithic Memories, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Birkner, John M., Chua, Hua-Thye
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US05/799,509
• Time in Patent Office: 533 Days
• Field of Search: 235/152, 235/156, 235/164, 307/207, 340/166 R, 340/900, 364/716
• US Class Current: 326/40
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H03K 19/17708 using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
• CPC Class Codes: H03K 19/17716 with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register H03K19/17712 takes precedence

Abstract

Programmable array logic circuitry is disclosed wherein the outputs from a field programmable AND gate array are connected, non-programmably, to specified OR gates. For greater architectural and operational flexibility, registered outputs, internal feedback to the AND gate array, input/output pin interchangeability, and means for allowing performance of arithmetical, as well as logic, operations, are provided.

Claims

1. A programmable integrated logic circuit array comprising:

(a) a plurality of groups of logical AND gates;

(b) a plurality of logical OR gates;

(c) non-programmable connections between the outputs from all of the AND gates within each of said groups of AND gates to inputs of predetermined and select individual ones of the logical OR gates;

(d) a matrix of electrical conductor lines comprising

(i) input lines, and

(ii) AND gate input lines for each of the AND gates within said plurality of groups of logical AND gates; and

(e) means for selectively connecting input lines and AND gate input lines to program a desired logical output from said OR gates.

2. A programmable integrated logic circuit array as in claim 1 including register means connected to the output of at least one of said logical OR gates for storing the logical state of the OR gate to which it is connected.

3. A programmable integrated logic circuit array as in claim 2 including means for connecting the output from each of said register means to selected ones of said input lines.

4. A programmable integrated logic circuit array as in claim 1 including gating means connected to the output of at least one of said OR gates, feedback means for connecting the output of each gating means to selected ones of said input lines;

and means for gating each of said gating means to either disable or enable said OR gate, said feedback means being operable as an input line when said OR gate is disabled.

5. A programmable integrated logic circuit array as in claim 4 wherein at least one of said gating means is permanently gated to either enable or disable said OR gate.

6. A programmable integrated logic circuit array as in claim 4 wherein at least one of said gating means is temporarily gated to either enable or disable said OR gate.

7. A programmable array of integrated logic circuitry comprising:

(a) a plurality of AND gates, each AND gate having a plurality of inputs and an output;

(b) a progrmmable matrix comprising a plurality of input lines and said inputs to said AND gates;

(c) a plurality of OR gates; and

(d) non-programmable electrical connections between the outputs of sub-pluralities of said AND gates and predetermined and select individual ones of said OR gates.

8. A programmable integrated logic circuit array as in claim 7 including register means connected to the output of at least one of said logical OR gates for storing the logical state of the OR gate to which it is connected.

9. A programmable integrated logic circuit array as in claim 8 including means for connecting the output from each of said register means to selected ones of said input lines.

10. A programmable integrated logic circuit array as in claim 7 including gating means connected to the output of at least one of said OR gates;

feedback means for connecting the output of each gating means to selected ones of said input lines; and

means for gating each of said gating means to either disable or enable said OR gate, said feedback means being operable as an input line when said OR gate is disabled.

11. A programmable integrated logic circuit array as in claim 10 wherein each of said gating means is permanently gated to either enable or disable said OR gate.

12. A programmable integrated logic circuit array as in claim 10 wherein each of said gating means is temporarily gated to either enable or disable said OR gate.

13. A programmable integrated logic circuit array comprising:

(a) a plurality of logical AND gates, each AND gate having a plurality of inputs and an output;

(b) a matrix comprising the inputs to said logical AND gates and a plurality of input lines;

(c) means for selectively connecting desired input lines with desired logical AND gate inputs;

(d) a plurality of logical OR gates;

(e) non-programmable connections from outputs of specified logical AND gates to inputs of an individual and select OR gate;

(f) register means connected to the output of at least one of said logical OR gates for storing the logical state of the OR gate to which it is connected.

14. A programmable integrated logic circuit array as in claim 13 including means for connecting the ouput from at least one of said register means to selected ones of said input lines.

15. A programmable integrated logic circuit array as in claim 14 including gating means connected to the output of at least one of said logical OR gates to which a register means is not connected feedback means for connecting the output of each of the gating means to selected ones of said input lines and means for gating each of said gating means to either disable or enable said OR gate, said feedback means being operable as an input line when said OR gate is disabled.

17. A programmable integrated logic circuit array as in claim 15 wherein at least one of said gating means is permanently gated to either enable or disable said OR gate.

16. A programmable integrated logic circuit array comprising:

(a) a plurality of logical AND gates, each AND gate having a plurality of inputs and an output;

(b) a matrix comprising the inputs to said logical AND gates and a plurality of input lines;

(c) means for selectively connecting desired input lines with desired logical AND gate inputs;

(d) a plurality of logical OR gates;

(e) means for connecting outputs from said logical AND gates to inputs to said OR gates;

(f) gating means connected to the output of at least one of said OR gates;

(g) feedback means for connecting the output of each of the gating means to selected ones of said input lines; and

(h) means for gating each of said gating means to either disable or enable said OR gate;

said feedback means being operable as an input line when said OR gate is disabled.

18. A programmable integrated logic circuit array as in claim 16 wherein at least one of said gating means is temporarily gated to either enable or disable said OR gate.

19. A programmable integrated logic circuit array as in claim 16 including register means connected to the output of at least one of said logical OR gates to which a gating means is not connected for storing the logical state of the OR gate to which it is attached.

20. A programmable integrated logic circuit array as in claim 19 including means for connecting the output of each of said register means to selected input lines.

21. A programmable integrated logic circuit array for performing arithmetic operations, comprising:

(a) a plurality of logical AND gates, each AND gate having a plurality of inputs and an output;

(b) a matrix comprising the inputs to said logical AND gates and a plurality of input lines;

(c) means for selectively connecting desired input lines with desired logical AND gate inputs;

(d) a plurality of logical OR gates;

(e) means for connecting outputs from said logical AND gates to inputs of said OR gates;

(f) a plurality of exclusive-OR gates whose inputs comprise at least a pair of said OR gates;

(g) register means connected to the outer of at least one of said logical exclusive-OR gates for storing the logical state of the exclusive-OR gate to which it is connected; and

(h) carry logic circuitry each having a pair of inputs, one input being connected to said register means and one input from an external input for providing carry signal information to said AND gate inputs.