Symmetrical cell layout for static RAM
First Claim
1. An integrated circuit memory comprising:
- a substrate of semiconductor material of a first conductivity type;
an array of memory cells fabricated on the substrate in rows and columns;
each cell of the array including first and second data storage transistors, first and second enabling transistors, and first and second impedance devices, each of the transistors having a gate, a source diffusion region, and a drain diffusion region formed in the substrate;
the gate of the second data storage transistor being electrically connected to the drain diffusion of the first data storage transistor, to the drain diffusion of the first enabling transistor, and to the first impedance device thereby defining a first data node in each cell of the array;
the gate of the first data storage transistor being electrically connected to the drain diffusion of the second data storage transistor, to the drain diffusion of the second enabling transistor, and to the second impedance device thereby defining a second data node in each cell of the array;
the drain diffusion of the first data storage transistor being formed in common with the drain diffusion of the first enabling transistor of each cell of the array;
the array including a first group of four of the cells disposed in mutual contiguous relation to each other in a first row and in a second row adjacent to the first row, and in a first column and in a second column adjacent to the first column,the source diffusions of the second data storage transistors of contiguous cells in the first and second rows of the first group being formed in common, respectively; and
,the first and second impedance devices of each cell of the first group being electrically connected together to form a drain supply node common to each cell of the group.
3 Assignments
0 Petitions
Accused Products
Abstract
A symmetrical structural layout for the principal components of each cell in a group of four mutually contiguous cells of an array of memory cells is disclosed. A common drain supply node is centrally disposed within the group and is coincident with the intersection of first and second mutually perpendicular axes of symmetry. Corresponding components of contiguous cells in each row and column are symmetrically disposed with respect to each of the first and second axes of symmetry. In a preferred embodiment, the principal components of each cell include a plurality of insulated gate field-effect transistors each having a source diffusion region and a drain diffusion region formed within the substrate and a plurality of impedance devices electrically connecting the common drain supply node to the drain diffusions of the transistors in each cell. The impedance devices extend radially from the common drain supply node into the interior of each cell, and at least one of the diffused regions of each transistor in each cell is formed in common with a diffused region of a transistor of a contiguous cell.
68 Citations
11 Claims
-
1. An integrated circuit memory comprising:
-
a substrate of semiconductor material of a first conductivity type; an array of memory cells fabricated on the substrate in rows and columns; each cell of the array including first and second data storage transistors, first and second enabling transistors, and first and second impedance devices, each of the transistors having a gate, a source diffusion region, and a drain diffusion region formed in the substrate; the gate of the second data storage transistor being electrically connected to the drain diffusion of the first data storage transistor, to the drain diffusion of the first enabling transistor, and to the first impedance device thereby defining a first data node in each cell of the array; the gate of the first data storage transistor being electrically connected to the drain diffusion of the second data storage transistor, to the drain diffusion of the second enabling transistor, and to the second impedance device thereby defining a second data node in each cell of the array; the drain diffusion of the first data storage transistor being formed in common with the drain diffusion of the first enabling transistor of each cell of the array; the array including a first group of four of the cells disposed in mutual contiguous relation to each other in a first row and in a second row adjacent to the first row, and in a first column and in a second column adjacent to the first column, the source diffusions of the second data storage transistors of contiguous cells in the first and second rows of the first group being formed in common, respectively; and
,the first and second impedance devices of each cell of the first group being electrically connected together to form a drain supply node common to each cell of the group. - View Dependent Claims (2, 3, 4, 5)
-
-
6. In an integrated circuit memory of the type including an array of memory cells fabricated on a semiconductor subtrate in rows and columns, each cell including principal components interconnected to store bits of binary data, an improved structural layout for the principal components of each cell in a group of four mutually contiguous cells of the array comprising:
-
a common drain supply node disposed substantially in the geometrical center of the group as defined by the intersection of a first centerline axis and a second centerline axis disposed substantially perpendicular to the first axis; and
,corresponding component of contiguous cells in each row of the group being symmetrically disposed with respect to each of the first and second axes. - View Dependent Claims (7, 8, 9, 10)
-
-
11. An integrated circuit memory comprising:
-
a substrate of semiconductor material doped with impurities of a first conductivity type; an array of memory cells fabricated on the substrate in input rows and output columns; the substrate within each cell of the array including first and second pairs of active surface areas surrounded by a substrate field area, the first pair being the situs of first and second data storage transistors, and the second pair being the situs of first and second enabling transistors; a strip of gate insulating material disposed over a portion of each active situs area; a diffusion of impurities of the opposite conductivity type disposed in the substrate beneath each active surface area on either side of the gate insulating strip thereby forming source and drain diffusion regions for each transistor, a nondiffused channel region being defined in the active substrate area beneath the gate insulating strip and between the source and drain diffusion regions, the source and drain diffusion regions of each transistor extending through the surrounding field regions of the substrate for predetermined distances; a first layer of electrical insulating material being disposed over the substrate field area of each cell and around but not over the active situs areas of each cell; a conductive gate strip deposited on each gate insulating strip, the conductive gate strips extending transversely with respect to the associated source and drain regions and across the surrounding field insulation; the conductive gate strips of the first and second enabling transistors of each cell of each input row being formed in common thereby defining a common row address line for each input row; the source diffusions of the first and second enabling transistors of each cell in a selected row being formed in common with the source diffusions of the first and second enabling transistors of contiguous cells of an adjacent row respectively; the conductive gate strips of the first and second data storage transistors of each cell extending transversely with respect to the associated diffused source and drain regions across the field insulation and being disposed in electrical contact with the drain diffusions of the second and first enabling transistors, respectively, and in electrical contact with the drain diffusions of the second and first data storage transistors of the same cell, respectively; first and second impedance means each having a first and second terminal portion, the first terminal portion being electrically connected to the drain diffusions of the first and second data storage transistors of each cell, respectively, thereby defining a first and second data node in each cell, the second terminal portions of the impedance means in each cell of a first group of four mutually contiguous cells being electrically connected together to define a common drain supply node; the source diffusions of the first data storage transistors of each cell in a second group of four mutually contiguous cells being formed in common thereby defining a first common source supply node, the cells of the second group being disposed in the adjacent rows in which the cells of the first group are disposed, one cell in each row being common to each of the first and second selected groups; the drain diffusion of the first data storage transistor of each cell being formed in common with the drain diffusion of the first enabling transistor of each cell; the source diffusion of the second data storage transistor of each cell being formed in common with the source diffusion of the second data storage transistor disposed in the contiguous cell of the same row and adjacent column thereby defining a second source supply node; a second insulating layer deposited over the first insulating layer, the row address line, gates strips and impedance devices; a first conductive strip deposited over the second insulating layer and extending transversely with respect to the row address lines across each row of cells, the first conductive strip being electrically connected to each of the first common source supply nodes defined by a plurality of the second groups, the mutually contiguous cells of each of the second groups being disposed in adjacent columns, thereby defining a first source supply line common to each cell in adjacent columns containing the second groups; a second conductive strip deposited over the second insulating layer and extending across each row of cells substantially parallel to the first conductive strip, the second conductive strip being electrically connected to the common source diffusions of first enabling transistors of contiguous cells in the column thereby defining a common data output line for each of the cells in the column; a third conductive strip deposited over the second insulating layer and extending across each row of cells substantially parallel to the second conductive strip, the second conductive strip being electrically connected to each of the second data nodes of each cell in the column thereby defining a common data complement output line for each of the cells in the column; a fourth conductive strip deposited over the second insulating layer and extending across each row of cells of the array and substantially parallel to the third conductive strip, the fourth conductive strip being electrically connected to each of the second source supply nodes of each cell in the column thereby defining a second source supply line common to each cell in the column; and
,a fifth conductive strip deposited over the second insulating layer and extending across each row of cells in the column, the fifth conductive strip being electrically connected to each of the common source supply nodes defined by a plurality of the first groups of cells, the mutually contiguous cells of each of the first selected groups being disposed inadjacent pairs of columns, thereby defining a drain supply line common to each cell in adjacent columns containing the first selected groups.
-
Specification