Bidirectional interface utilizing read-only memory, decoder and multiplexer

• US 4,127,896 A
• Filed: 08/10/1977
• Issued: 11/28/1978
• Est. Priority Date: 08/10/1977
• Status: Expired due to Term

• Current Assignee: Allied Corp. (Honeywell International Inc.)
• Original Assignee: Bunker Ramo Corporation (Honeywell International Inc.)
• Inventors: Raslavsky, John M. III
• Primary Examiner(s): Chapnick, Melvin B.
• Application Number:
  US05/823,432
• Time in Patent Office: 475 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 340/347 DD
• US Class Current: 703/26
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B

Abstract

An apparatus matches control code signals and data signals between data processing units which employ different control code formats. The interface is especially suitable for use between a computer bus interface and a controller or between two separate controllers. It employs read-only memory circuits which convert control code signals from the computer bus into discrete controls and commands compatible with the code format of the controller. The read-only memory circuits are programmable to allow looping programs to be implemented.

Claims

1. An interface system for matching control code signals and data signals between a data processing unit and a controller which employ different control code formats, comprising:

a control register for receiving control code signals from the data processing unit and having an input and an output;

a first read-only memory circuit responsive to the output of said control register and programmed to provide discrete control signals corresponding to the control code signals in said control register;

a second read-only memory circuit responsive to the output of said control register and programmed to convert the control code signals in said control register into corresponding commands in the control code format of the controller;

clock means initiated upon loading of the control code signals into said control register for operating said first and second read-only memory circuits;

decoder means responsive to the discrete control signals of said first read-only memory circuit for applying discrete controls to the controller to condition its registers to receive commands or data signals and for generating a select signal; and

means responsive to said select signal generated by said decoder means for selectively applying either commands from said second read-only memory circuit or data signals from the data processing unit to the controller.

2. The interface system of claim 1, wherein:

said second read-only memory circuit is programmed to provide jump address commands to implement looping programs.

3. The interface system of claim 2, which includes:

means for sampling the response of the controller to condition said clock means to respond to the jump address commands from the second read-only memory circuit.

4. The interface system of claim 1, which includes:

a temporary storage register operable under the control of said decoder means for receiving and storing data signals from the data processing unit for transmission to the controller.

5. The interface system of claim 4, wherein:

said temporary storage register is also operable under the control of said decoder means to receive and store data signals from the controller for transmission to the data processing unit.

6. An emulation interface for matching control code signals and data signals between a computer bus interface and a controller which employ different, fixed control code formats, comprising:

a control register for receiving control code signals from the computer bus interface and having an input and an output;

a first read-only memory circuit having its most significant binary inputs responsive to the output of said control register and programmed to provide discrete control signals corresponding to the control code signals from the computer bus interface;

a second read-only memory circuit having its most significant binary inputs responsive to the output of said control register and programmed to convert the control code signals of the computer bus interface into corresponding commands in the control code format of the controller;

a binary counter initiated by the computer bus interface upon loading of the control code signals into said control register, said binary counter having its output coupled to the least significant binary inputs of said first and second read-only memory circuits for indexing said first and second read-only memory circuits;

a command decoder responsive to the output of said first read-only memory circuit for converting its discrete control signals into the control code format of the controller and applying discrete controls to the controller to condition its registers to receive commands or data signals, and for generating a select signal; and

a multiplexer having first inputs for receiving command signals from said second read-only memory circuit and data signals from the computer bus interface, a second input for receiving a signal from said command decoder, and an output coupled to the controller for selectively applying either commands from said second read-only memory circuit or data signals from the computer bus interface to the controller under the control of said select signal generated by said command decoder.

7. The emulation interface of claim 6 wherein:

said second read-only memory circuit is programmed to provide jump address commands which are applied to said binary counter to operate said first and second read-only memory circuits to implement looping programs.

8. The emulation interface of claim 7, which includes:

means for sampling the response of the controller to the discrete controls, commands and data signals to condition said binary counter to respond to the jump address commands from said second read-only memory circuit.

9. The emulation interface of claim 6, which includes:

a temporary storage register operable under the control of said command decoder for receiving and storing data signals from the computer bus interface for transmission to the controller.

10. The emulation interface of claim 9, wherein:

said temporary register is also operable under the control of said command decoder to receive and store data signals from the controller for transmission to the computer bus interface.