Fabrication method for integrated circuits with polysilicon lines having low sheet resistance

• US 4,128,670 A
• Filed: 11/11/1977
• Issued: 12/05/1978
• Est. Priority Date: 11/11/1977
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gaensslen, Fritz H.
• Primary Examiner(s): Weiffenbach, Cameron K.
• Application Number:
  US05/850,586
• Time in Patent Office: 389 Days
• Field of Search: 427/84, 427/86, 427/90, 427/91, 427/93, 427/96, 427/88, 427/272, 357/15, 357/67
• US Class Current: 438/592
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/321 After treatment
• CPC Class Codes: H01L 21/76889 by forming silicides of refractory metals
• CPC Class Codes: H01L 23/53271 containing semiconductor material, e.g. polysilicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/147 Silicides

Abstract

A method and structure for polysilicon lines which include a silicide layer for providing a low sheet resistance. The invention may be employed in a polysilicon gate MOSFET process for integrated circuits as well as other integrated structures. In the method a first layer of polysilicon is deposited followed by a deposition of a metal of the silicide forming type. Another polysilicon layer is then deposited on top of the silicide forming metal to produce a three layer structure. The three layer structure is subjected to heat, for example, during the reoxidation step in a gate fabrication process, the metal reacts with the polysilicon at two reaction fronts to form a silicide. The resultant silicide has a much lower resistivity than doped polysilicon and therefore provides a second conductive layer which can be used more compatibly and efficiently in connection with the normal metal layer employed in integrated circuits to give a two-dimensional degree of freedom for the distribution of signals.

Claims

1. A method for fabricating an electrically conductive combined polysilicon and metal silicide structure for integrated circuits comprising the steps of depositing a first layer of polysilicon on a substrate,

depositing a layer of silicide forming metal on said first polysilicon layer,

depositing a second layer of polysilicon on said silicide forming metal layer,

and heating said polysilicon and metal structure to cause said metal layer to react with said first and second polysilicon layers to form a metal silicide layer intermediate said first and second polysilicon layers.

2. A method for fabricating a polysilicon and metal silicide structure according to claim 1 wherein said silicide forming metal is selected to produce an electrically conductive silicide having a resistivity substantially at least an order of magnitude lower than the resistivity of said polysilicon.

3. A method according to claim 1 wherein said silicide forming metal is molybdenum.

4. A method according to claim 1 wherein said silicide forming metal is tungsten.

5. A method according to claim 1 wherein said silicide forming metal is titanium.

6. A method for fabricating a polysilicon and metal silicide structure according to claim 1 wherein said heating step also produces a layer of oxide on the upper surface of said second layer of polysilicon.

7. A method for fabricating a polysilicon and metal silicide structure according to claim 6 further including the step of forming a metal layer on said oxide layer.

8. A method according to claim 7 wherein said metal layer is composed of aluminum.

9. A method for fabricating a gate electrode for an integrated circuit comprising the steps of depositing a first oxide layer on a semiconductor substrate,

depositing a first layer of polysilicon on said first oxide layer,

depositing a layer of silicide forming metal of said first polysilicon layer,

depositing a second layer of polysilicon on said silicide forming metal layer to form a three-layer structure disposed on said first oxide layer on said semiconductor substrate,

masking and delineating said three layer structure to form a gate electrode element,

heating said combination to form a second oxide layer over said gate electrode element and to cause said silicide forming metal to react with said first and second polysilicon layers to form a silicide layer intermediate said first and second polysilicon layers.

10. A method for fabricating a polysilicon and metal silicide structure according to claim 9 wherein said silicide forming metal is selected to produce an electrically conductive silicide having a resistivity substantially at least an order of magnitude lower than the resistivity of said polysilicon.

11. A method according to claim 10 further including the step of forming a metal layer over said second oxide layer.

12. A method according to claim 11 wherein said metal layer is composed of aluminum.