Semiconductor integrated circuit devices having inverted frustum-shape contact layers

• US 4,128,845 A
• Filed: 07/19/1976
• Issued: 12/05/1978
• Est. Priority Date: 07/28/1975
• Status: Expired due to Term

• Current Assignee: Nippon Telegraph and Telephone Corporation
• Original Assignee: Nippon Telegraph and Telephone East Corporation (Nippon Telegraph and Telephone Corporation)
• Inventors: Sakai, Tetsushi
• Primary Examiner(s): Miller, Jr., Stanley D.
• Assistant Examiner(s): Davie, James W.
• Application Number:
  US05/706,596
• Time in Patent Office: 869 Days
• Field of Search: 357/40, 357/34, 357/59, 357/51, 357/55, 357/68
• US Class Current: 257/588
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 23/53271 containing semiconductor material, e.g. polysilicon
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Inverted frustum shaped polycrystalline semiconductor layers are formed on the emitter and collector regions provided on one surface of a semiconductor substrate, and conductor layers are applied on the upper surfaces of the polycrystalline semiconductor surfaces to form emitter and collector electrodes thus providing a bipolar transistor for the integrated circuit device.

Claims

1. A semiconductor integrated circuit device including a bipolar transistor comprising a semiconductor substrate, a collector region, a base region and an emitter region which are spaced apart and formed at one surface of said semiconductor substrate, a plurality of inverted frustum-shape polycrystalline semiconductor contact layers having raised upper larger cross sectional surfaces and lower smaller cross sectional surfaces, one of said inverted frustum-shape polycrystalline semiconductor contact layers being formed on and in direct contact with each of said emitter region and said collector region, respectively, a first insulating film covering the raised side surfaces of said inverted frustum-shaped polycrystalline semiconductor contact layers and overlying the upper surface portions of said substrate which are included substantially within the vertical projection of the raised upper larger cross sectional surfaces of the inverted frustum-shape polycrystalline semiconductor contact layers down upon the upper surface of said substrate, a second insulating film covering the surface portions of said one surface of said substrate other than those areas covered by said first insulating film, the contact layers and said base region, a base electrode formed on said base region below the plane of the raised upper larger cross sectional surfaces of the inverted frustum-shape polycrystalline semiconductor contact layers and an emitter electrode and a collector electrode formed on the upper surfaces of the respective inverted frustum-shape polycrystalline semiconductor contact layers.

2. A semiconductor integrated circuit device according to claim 1 wherein the inverted frustum-shape polycrystalline semiconductor contact layers each are comprised of two layers, a polycrystalline silicon layer having a high dopant level comprising the lower smaller cross sectional surfaces thereof and a non-doped semiconductor polycrystalline layer comprising the raised upper larger cross sectional surfaces thereof, the two layers having been differentially etched by an etchant to form the inverted frustum-shape and thereafter heated to form a substantially homogeneous contact layer.

3. A semiconductor integrated circuit device according to claim 1 wherein at least a part of said second insulating film covering the upper surface portions of said substrate immediately surrounding said emitter inverted frustum-shape contact layer extends onto and overlies a peripheral edge portion of said base region.

4. A semiconductor integrated circuit device according to claim 3 wherein the inverted frustum-shape polycrystalline semiconductor contact layers each are comprised of two layers, a polycrystalline silicon layer having a high dopant level comprising the lower smaller cross sectional surfaces thereof and a non-doped semiconductor polycrystalline layer comprising the raised upper larger cross sectional surfaces thereof, the two layers having been differentially etched by an etchant to form the inverted frustum-shape and thereafter heated to form a substantially homogeneous contact layer.

5. The semiconductor integrated circuit device according to claim 4 which further comprises at least one additional area of polycrystalline semiconductor layer disposed over at least a portion of said second insulating film and a metal conductor disposed on said additional area of polycrystalline semiconductor layer, a portion of said last-mentioned metal conductor being interrupted by a third insulating film thereby enabling use of said additional area of polycrystalline semiconductor layer as a resistor.

6. The semiconductor integrated circuit device according to claim 1 which further comprises at least one additional area of polycrystalline semiconductor layer disposed over at least a portion of said second insulating film and a metal conductor disposed on said additional area of polycrystalline semiconductor layer, a portion of said last-mentioned metal conductor being interrupted by a third insulating film thereby enabling use of said additional area of polycrystalline semiconductor layer as a resistor.

7. The semiconductor integrated circuit device according to claim 1 which further comprises interconnecting conductors connected to said collector and emitter electrodes, and an interconnecting conductor to said base electrode, said interconnecting conductors being spaced from each other by a step-shaped portion of the first insulating film covering the side surfaces of said inverted frustum-shape polycrystalline semiconductor contact layers.

8. The semiconductor integrated circuit device according to claim 1 which further comprises a first interconnecting conductor disposed on said second insulating film adjacent at least one of said inverted frustum-shape polycrystalline semiconductor contact layers, a third insulating film overlying said one polycrystalline semiconductor contact layer and said first interconnecting conductor, and a second interconnecting conductor overlying said third insulating film and extending through openings in said third insulating layer to contact and interconnect the electrode on said one polycrystalline semiconductor contact layer and said first interconnecting conductor.

9. The semiconductor integrated circuit device according to claim 1 which further comprises a first interconnecting conductor disposed on said second insulating film adjacent at least one of said inverted frustum-shape polycrystalline semiconductor contact layers, and a second interconnecting conductor directly covering the electrode on said one polycrystalline semiconductor contact layer and said first interconnecting conductor for interconnecting them.

10. The semiconductor integrated circuit device according to claim 1 wherein a step-shaped raised polycrystalline semiconductor member is formed on said second insulating film, and said integrated circuit device further comprises an insulating film covering at least the raised side surfaces of said step-shaped polycrystalline semiconductor member, and an interconnecting conductor disposed on said second insulating film and extending over and contacting the upper surfaces of said step-shaped polycrytalline semiconductor member.