Computer vector register processing
First Claim
1. Vector processing apparatus for a computer having a main memory, comprising:
- a plurality of vector registers each including means for holding a plurality of elements of an ordered set of data;
at least one arithmetic or logical functional unit having an input for receiving operands and an output for delivering results, said functional unit including segmented means for holding data for operations not yet completed while receiving operands for successive operations;
path select means associated with said vector registers and responsive to program instructions for selectively connecting individual vector registers for transmission of data to or from said main memory, and for selectively connecting individual vector registers for transmitting data as operands to a functional unit and for receiving results from a functional unit; and
control means associated with said vector registers and responsive to program instructions, said control means being operative in conjunction with a vector register selected as an operand register in a vector processing operation to successively transmit the elements of the ordered set of data from the vector register to a functional unit on successive clock periods, said control means being operative in conjunction with a vector register selected as a result register in a vector processing operation to receive and store successive results transmitted from a functional unit as elements of an ordered set of data representing a result vector, on successive clock periods following delivery of the first result from the functional unit.
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Accused Products
Abstract
Vector processing in a computer is achieved by means of a plurality of vector registers, a plurality of independent fully segmented functional units, and means for controlling the operation of the vector registers. Operations are performed on data from vector register to functional unit and back to vector register with minimal delay, rather than memory to functional unit and return to memory with its attendant much greater start-up delays. Data may be bulk transferred between memory and some vector registers while other vector registers are involved in vector processing with one or more functional units. In vector processing elements of one or more vector registers are successively transmitted as operands to a functional unit at a rate of one per clock period, and results are transmitted from a functional unit to a receiving vector register at the same rate. In a chaining mode of operation, the elements in a result vector register become available for immediate and simultaneous transmission as operands to another functional unit. In this mode, more than one result can be obtained per clock period.
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Citations
12 Claims
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1. Vector processing apparatus for a computer having a main memory, comprising:
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a plurality of vector registers each including means for holding a plurality of elements of an ordered set of data; at least one arithmetic or logical functional unit having an input for receiving operands and an output for delivering results, said functional unit including segmented means for holding data for operations not yet completed while receiving operands for successive operations; path select means associated with said vector registers and responsive to program instructions for selectively connecting individual vector registers for transmission of data to or from said main memory, and for selectively connecting individual vector registers for transmitting data as operands to a functional unit and for receiving results from a functional unit; and control means associated with said vector registers and responsive to program instructions, said control means being operative in conjunction with a vector register selected as an operand register in a vector processing operation to successively transmit the elements of the ordered set of data from the vector register to a functional unit on successive clock periods, said control means being operative in conjunction with a vector register selected as a result register in a vector processing operation to receive and store successive results transmitted from a functional unit as elements of an ordered set of data representing a result vector, on successive clock periods following delivery of the first result from the functional unit. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. The method of processing vectors in a computer having a main memory, a plurality of vector registers and at least one segmented arithmetic or logical functional unit for receiving successive inputs of operands while holding data for operations still being completed and for delivering successive operation results, comprising the steps of:
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intermittently transmitting data from the main computer memory to vector registers for storage as a plurality of elements of an ordered set of data; selecting from said plurality of vector registers at least one vector register to provide operands and one vector register to receive results; successively transmitting the elements of the ordered set of data from the selected operand vector register to a functional unit on successive clock periods; and successively transmitting results produced by the functional unit as elements of an ordered set to the selected result vector register on successive clock periods following delivery of the first result from the functional unit. - View Dependent Claims (9, 10, 11, 12)
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Specification