Raster scan type CRT display system having an image rolling function

• US 4,129,859 A
• Filed: 02/08/1977
• Issued: 12/12/1978
• Est. Priority Date: 02/12/1976
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Sato, Nobuo, Iwamura, Masahiro, Hamada, Nagaharu, Hara, Toshitaka
• Primary Examiner(s): Curtis, Marshall M.
• Application Number:
  US05/766,728
• Time in Patent Office: 672 Days
• Field of Search: 340/324 A, 340/324 AD, 364/200 MS File, 364/200, 364/900, 178/30
• US Class Current: 345/686
• CPC Class Codes: G09G 5/343 for systems having a character code-mapped display memory

Abstract

A raster scan type CRT display system is disclosed which has a randomly accessable refresh memory. The display system comprises column and row start address registers for defining a read start address for the refresh memory, column and row address counters for counting the contents of the column and row start address registers as start positions to generate a read address of the refresh memory for display, column and row cursor registors for defining a data entry position on a CRT screen, and column and row address generators for generating an entry address for the refresh memory based on the contents of the column and row start address registers and the contents of the column and row cursor registers, whereby a rolling or shifting of the image is effected and the refresh memory can be accessed by a processor for read/write operation without the need to monitor the image rolling.

Claims

1. A raster scan type CRT display system having an image rolling function wherein coded data stored in a refresh memory is read out in synchronism with the scan of a CRT display and is displayed on a CRT viewer in accordance with a sequence of display column and row addresses, said CRT viewer having a display capacity of m columns by n rows and said refresh memory can be accessed by a processor for read/write operation, said display system comprising:

said refresh memory being randomly accessable and having a storage capacity of at least m x n characters;

a timing control circuit for generating timing signals which include character clock pulses and line clock pulses;

column and row start address registers for defining a read start address for said refresh memory;

column and row cursor address registers for defining an address for the read/write operation by said processor to said refresh memory;

a modulo m address counter to which the content of said column start address register is preset for each horizontal scan and which counts up the character clock pulses from said timing control circuit starting from the preset count to produce a sequence of display column addresses; and

a modulo n address counter to which the content of said row start address register is preset for each vertical scan and which counts up the line clock pulses from said timing control circuit starting from the preset count to produce a sequence of display row addresses.

2. A raster scan type CRT display system according to claim 1, further comprising address generators for generating the column and row read/write addresses for said refresh memory based on the contents of said column and row cursor address registers and the contents of said column and row start address registers.

3. A raster scan type CRT display system according to claim 2, wherein each of said column and row address generators includes a first adder for summing the content of the corresponding cursor address register with the content of the corresponding start address register, a comparator for comparing an output of said first adder with the number m or n of the horizontal or vertical displayed characters to produce a "1" output when the output of said first adder is equal to or greater than m or n, a complementor for producing a complement of the number m or n of the horizontal or vertical displayed characters only when the output of said comparator is "1", and a second adder for summing the output of said first adder with the output of said complementer to produce the read/write address.

4. A raster scan type CRT display system according to claim 2, wherein each of said column and row address generators includes an adder for summing the content of the corresponding cursor address register with the content of the corresponding start address register, and a read only memory responsive to an output of said adder for producing a read/write address for said refresh memory determined by said output of said adder.

5. A raster scan type CRT display system wherein coded data stored in a refresh memory is read out in synchronism with the scan of a CRT display and is displayed on a CRT viewer having a display capacity of m columns by n rows and said refresh memory can be accessed by a processor for read/write operation, said display system comprising:

said refresh memory having a storage capacity of at least m x n characters;

a timing control circuit for generating timing signals which include character clock pulses and line clock pulses;

column and row start address registers for defining a read start address for said refresh memory;

said processor connected to said CRT display system through an interface to access to said refresh memory for the read/write operation;

a keyboard for issuing a read/write command to said processor through said interface;

column and row cursor address registers for defining an address for the read/write operation by said processor to said refresh memory;

a modulo m address counter to which the content of said column start address register is preset for each horizontal scan and which counts up the character clock pulses from said timing control circuit starting from the preset count to produce a sequence of display column addresses;

a modulo n address counter to which the content of said row start address register is preset for each vertical scan and which counts up the line clock pulses from said timing control circuit starting from the preset count to produce a sequence of display row addresses;

first adders for summing the contents of said column and row cursor address registers with the contents of said column and row start address registers respectively;

comparators for comparing the respective outputs of said first adders with the numbers m and n of the horizontal and vertical displayed characters respectively, to produce "1" outputs when the respective output of said first adders is equal to or greater than m or n respectively;

complementers for producing complement outputs of the numbers m and n of the horizontal and vertical displayed characters only when the respective output of said comparators is "1";

second adders for summing respective outputs of said first adders with the respective outputs of said complementers to produces the read/write address;

a character generator for generating a character signal corresponding to coded data read from said refresh memory;

a parallel-serial converter for converting the parallel character signal from said character generator to a serial character signal; and

said CRT viewer having a display capacity of m columns by n rows.