Programmable write-once, read-only semiconductor memory array using SCR current sink and current source devices

• US 4,130,889 A
• Filed: 05/02/1977
• Issued: 12/19/1978
• Est. Priority Date: 05/02/1977
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Monolithic Memories, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Chua, Hua-Thye
• Primary Examiner(s): Hecker, Stuart N.
• Assistant Examiner(s): McElheny, Donald
• Application Number:
  US05/792,940
• Time in Patent Office: 596 Days
• Field of Search: 340/173 SP, 307/238, 307/252 A, 307/252 G, 307/270, 307/299 B, 307/305, 365/96, 365/105, 365/94, 365/103, 365/189, 365/242, 365/243
• US Class Current: 365/96
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H10B 20/10 ROM devices comprising bipolar components

Abstract

This disclosure relates to a programmable write-once, read-only semiconductor memory array which has an improved current source for each bit line and an improved current sink for each Word line. This programmable write-once, read-only semiconductor memory array utilizes a SCR (PNPN or NPNP) or the end of each Word line of the array to function as a current sink to minimize voltage drop on the Word line and a SCR (PNPN or NPNP) on each Bit line of the array for current sourcing purposes. This disclosure also relates to an integrated SCR (PNPN or NPNP) for use with a plurality of connected semiconductor devices to provide either a current sourcing or current sinking or drawing function for the plurality of connected semiconductor devices.

Claims

1. A programmable semiconductor memory array comprising, in combination, a plurality of memory cells interconnected to provide a memory array, and a group of Word lines and a group of Bit lines, each of said memory cells being connected to one of said group of Word lines and one of said group of Bit lines, each of said memory cells having a first electrical state prior to receiving a writing signal and a different second electrical state after receiving a writing signal, and silicon controlled rectifier means connected to each line of said group of Word lines and to each line of said group of Bit lines to provide the functions of drawing current from said group of Word lines and sourcing current to said group of bit lines and to the memory cells connected to said silicon controlled rectifier means, said silicon controlled rectifier means connected to each line of said group of word lines being located at the opposite end of the word line from a word driver.

2. A programmable semiconductor memory array in accordance with claim 1 wherein said group of Word lines being high conductivity semiconductor lines, said group of Bit lines being metal lines overlying said high conductivity semiconductor lines.

3. A programmable semiconductor memory array in accordance with claim 2 wherein said silicon controlled rectifier means comprising a PNPN device.

4. A programmable semiconductor memory array in accordance with claim 3 wherein said PNPN device comprising a PNP transistor portion connected to a NPN transistor portion and having the base of said PNP transistor portion being the collector of said NPN transistor portion with the collector of said PNP transistor portion being the base of said NPN transistor portion, said emitter of said NPN transistor portion being connected to one of said group of metal Bit lines.

5. A programmable semiconductor memory array in accordance with claim 1 wherein said silicon controlled rectifier means comprising a PNPN device.

6. A programmable semiconductor memory array in accordance with claim 5 wherein said PNPN device comprising a PNP transistor portion connected to a NPN transistor portion and having the base of said PNP transistor portion being the collector of said NPN transistor portion with the collector of said PNP transistor portion being the base of said NPN transistor portion, said base of said PNP transistor portion and said collector of said NPN transistor portion of said PNPN device being connected to one of said group of Word lines.

7. A programmable semiconductor memory array in accordance with claim 6 wherein each said emitter of said PNP transistor portion of each said PNPN device connected to each of said Word lines being connected together by a common metal line, said base of said NPN transistor portion and said collector of said PNP transistor portion of each Word line PNPN device being connected to ground, said emitter of said NPN transistor portion of each Word line PNPN device being connected to ground.

8. A programmable semiconductor memory array in accordance with claim 7 wherein said emitter of said PNP transistor portion and said base of said NPN transistor portion of each said PNPN device connected to each of said Word lines being a diffused base type region of NPN bipolar transistor, said base of said PNP transistor portion and said collector of said NPN transistor portion of each said PNPN device connected to each of said Word lines being an epitaxial collector type region of a NPN bipolar transistor, said emitter region of said NPN transistor portion of each said PNPN device connected to each of said Word lines being an emitter type diffused region of a NPN bipolar transistor.

9. A programmable semiconductor memory array in accordance with claim 8 wherein said Word lines comprising an emitter type diffused region of a NPN bipolar transistor located in said epitaxial collector type region.

10. A programmable semiconductor memory array in accordance with claim 5 wherein said PNPN device comprising a PNP transistor portion connected to a NPN transistor portion and having the base of said PNP transistor portion being the collector of said NPN transistor portion with the collector of said PNP transistor portion being the base of said NPN transistor portion, said emitter of said NPN transistor portion being connected to one of said group of Bit lines.

11. A programmable semiconductor memory array in accordance with claim 10 wherein said emitter of said PNP transistor portion of said PNPN device connected to each of said Bit lines being connected together by a common metal line, said base of one PNP transistor portion of each said Bit line PNPN device being connected to the collector regions of the NPN transistor portions of a plurality of PNPN devices individually connected to a plurality of said Bit lines, said collector of said one PNP transistor portion being connected to base regions of said plurality of PNPN devices, said base and collector regions of said one PNP transistor portion being shared with a plurality of NPN transistor portions to provide said plurality of PNPN devices.

12. A programmable semiconductor memory array in accordance with claim 11 wherein said emitters of said PNP transistor portions and said bases of said NPN transistor portions of said plurality of PNPN devices connected to said plurality of Bit lines being a diffused base type region of a NPN bipolar transistor, said bases of said PNP transistor portions and said collectors of said NPN transistor portions of each of said plurality of PNPN devices connected to said plurality of Bit lines being an epitaxial collector type region of a NPN bipolar transistor, said emitter region of said NPN transistor portions of each of said plurality of PNPN devices connected to said plurality of Bit lines being an emitter type diffused region of a NPN bipolar transistor.

13. A programmable semiconductor memory array in accordance with claim 12 wherein said Bit lines comprising metal lines, each of said metal Bit lines being connected to said emitters of said NPN transistor portions of said plurality of PNPN devices connected to said plurality of Bit lines.

14. A programmable semiconductor memory array in accordance with claim 10 wherein said PNPN device of said silicon controlled rectifier means connected to each line of said Word lines comprising a PNP transistor portion connected to a NPN transistor portion and having the base of said PNP transistor portion being the collector of said NPN transistor portion with the collector of said PNP transistor portion being the base of said NPN transistor portion, said base of said PNP transistor portion and said collector of said NPN transistor portion of said PNPN device being connected to one of said group of Word lines.

15. A programmable semiconductor memory array in accordance with claim 14 wherein each said emitter of said PNP transistor portion of said PNPN device connected to each of said Word lines being connected together by a common metal line, said base of said NPN transistor portion and said collector of said PNP transistor portion of each Word line PNPN device being connected to ground, said emitter of said NPN transistor portion of each Word line PNPN device being connected to ground, said emitter of said PNP transistor portion and said base of said NPN transistor portion of each said Word line PNPN device being a diffused base type region of a NPN bipolar transistor, said base of said PNP transistor portion and said collector of said NPN transistor portion of each said Word line PNPN device being an epitaxial collector type region of a NPN bipolar transistor, said emitter region of said NPN transistor portion of each said Word line PNPN device being an emitter type diffused region of a NPN bipolar transistor, said Word lines comprising an emitter type diffused region of a NPN bipolar transistor located in said epitaxial collector type region, each of said emitters of said PNP transistor portion of each said PNPN device connected to each of said Bit lines connected together by a common metal line, said base of one PNP transistor portion of one of said Bit line PNPN devices being connected to collector regions of said NPN transistor portions of a plurality of Bit line PNPN devices individually connected to a plurality of said Bit lines, said collector of said one PNP transistor portion being connected to base regions of said plurality of Bit line PNPN devices, said base and collector regions of said one PNP transistor portion being shared with a plurality of NPN transistor portions to provide said plurality of Bit line PNPN devices, said emitters of said PNP transistor portions and said bases of said NPN transistor portions of said plurality of Bit line PNPN devices being a diffused base type region of a NPN bipolar transistor, said bases of said PNP transistor portions and said collectors of said NPN transistor portions of each of said plurality of Bit line PNPN devices being an epitaxial collector type region of a NPN bipolar transistor, said emitter region of said NPN transistor portions of each of said plurality of Bit line PNPN devices being an emitter type diffused region of a NPN bipolar transistor, and said Bit lines comprising metal lines, each of said metal Bit lines being connected to said emitters of said NPN transistor portions of said plurality of Bit line PNPN devices.