Method of semiconductor solar energy device fabrication

• US 4,131,488 A
• Filed: 04/25/1977
• Issued: 12/26/1978
• Est. Priority Date: 12/31/1975
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Pryor, Robert A., Lesk, Israel A.
• Primary Examiner(s): Dean, R.
• Assistant Examiner(s): Roy, Upendra
• Application Number:
  US05/792,438
• Time in Patent Office: 610 Days
• Field of Search: 136/89, 357/30, 29/572, 148/1.5
• US Class Current: 438/71
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 31/02168 the coatings being antireflective or having enhancing optical properties for the solar cells
• CPC Class Codes: H01L 31/022425 for solar cells
• CPC Class Codes: H01L 31/02363 of the semiconductor body itself, e.g. textured active layers
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy

Abstract

This disclosure relates to a semiconductor solar energy device which is of the PN-type and utilizes a dielectric anti-reflective coating on the side of the device that faces the sunlight. The fabrication techniques used in making this semiconductor device include the use of a rough or textured pyramid shaped silicon surface beneath the anti-reflective coating to increase solar cell efficiency. Also, ion implantation is used to form the PN junction in the device. The ion implanted region located on the side of the device that is subjected to the sunlight is configured in order to permit metal ohmic contact to be made thereto without shorting through the doped region during sintering of the metal contacts to the semiconductor substrate. The dielectric anti-reflective coating, in one embodiment, is a composite of silicon dioxide and silicon nitride layers. The device is designed to permit solder contacts to be made to the P and N regions thereof without possibility of shorting to semiconductor regions of opposite type conductivity.

Claims

1. A process for forming a semiconductor solar energy device comprising the steps of:

providing a silicon wafer of a first conductivity type with two major surfaces;

introducing a doping impurity of said first conductivity type into both major surfaces simultaneously;

forming an oxide layer on both major surfaces following the introduction of said doping impurities;

removing said oxide layer from a first major surface of said wafer;

treating said first major surface to form a textured pyramidal surface structure while masking a second major surface opposite said first major surface from said texture treating;

forming a thin layer of silicon dioxide in contact with said first major surface;

forming a thin layer of silicon nitride on said layer of silicon dioxide to form an antireflective coating; and

forming a shallow layer of semiconductor material of a second conductivity type opposite said first conductivity type of said first major surface.

2. A process according to claim 1 where said thin layer of silicon dioxide is formed by thermal oxide growth.

3. A process according to claim 1 where said shallow layer of semiconductor material of second conductivity type is formed by ion implantation.

4. A process according to claim 1 further including:

opening at least one hole through said silicon nitride and said silicon dioxide layers, ion implanting through said hole and said nitride and oxide layers to form said shallow layer of semiconductor material of said second conductivity type.

5. The process of claim 4, where said shallow layer is deeper under said hole than under said antireflective coating.

6. A process for the fabrication of a semiconductor solar energy comprising the steps of forming layers of enhanced conductivity on both surfaces of a semiconductor substrate of one type conductivity, selectively masking one of said surfaces, etching the other of said surfaces to remove one of said layers of enhanced conductivity and provide a pyramidal surface texture, forming a thin layer of silicon dioxide on said other surface and a thicker layer of silicon nitrite on said layer of silicon cioxide to provide an antireflective coating of said device, and forming a thin layer of second conductivity type opposite said one type conductivity under said antireflective coating.

7. The process of claim 6, further including forming at least one aperture in said antireflective coating and forming a region of said second conductivity type beneath said aperture.

8. The process of claim 6, where the forming of said thin layer of second conductivity type is effected by ion implantation, and further including shadow masking of the periphery of said substrate to prevent said thin layer from extending to the sides of the substrate.

9. The process of claim 6 where said selective masking prevents the texturing of said one surface.

10. The process of claim 7, where said region is coextensive with said aperture.

11. The process of claim 7, where said region of second conductivity type penetrates said substrate further than said thin layer of second conductivity type.