Communication system including addressing apparatus for use in remotely controllable devices

• US 4,131,881 A
• Filed: 09/12/1977
• Issued: 12/26/1978
• Est. Priority Date: 09/12/1977
• Status: Expired due to Term

• Current Assignee: Paul B. Robinson
• Original Assignee: Paul B. Robinson
• Inventors: Robinson, Paul B.
• Primary Examiner(s): Pitts, Harold I.
• Application Number:
  US05/832,795
• Time in Patent Office: 470 Days
• Field of Search: 340/167 R, 340/150, 340/151, 340/310 A, 340/163
• US Class Current: 340/9.1
• CPC Class Codes: H04Q 9/14 Calling by using pulses

Abstract

A data communication system includes apparatus for use in each of a plurality of simultaneously addressable terminal units. Means are provided for recognizing a large number of addresses to allow the selective addressing of any single terminal unit, simultaneous addressing of all terminal units, or the selective simultaneous addressing of various groups and sets of terminal units.

Claims

1. In a data communication system of the type including a plurality of simultaneously addressable remote terminal units in communication with a message generator, each message having an address field of a specified number of binary bits, combinations of which specify terminal unit addresses and a mode field containing at least one binary bit for specifying an address mode, apparatus in each of said remote terminal units for recognizing a plurality of addresses comprising:

(a) storage means for receiving messages from said message generator, said storage means having an address portion and a mode portion for storing the binary bits of the address and mode fields respectively of a received message;

(b) means for generating address signals representative of addresses assigned to the individual remote terminal units, the number of assignable addresses corresponding in number to at least the maximum number specifiable by the address field bits of said messages;

(c) comparator means in communication with the address portion of said storage means and said means for generating address signals, said comparator means selectively generating at least first and second output selection signals when a comparison exists between the contents of the address portion and an assigned address specified by said address signals; and

(d) gating means responsive to specified binary bits of the address field and the mode field bit from said storage means and to said at least first and second output selection signals from said comparator means, said gating means selectively generating a terminal unit address enable signal for use by the respective terminal units in response to,

(i) a first message received by said storage means to simultaneously address all terminal units in accordance with a predetermined combination of the specified binary bits of the address field when the mode field bit is in a first binary state,

(ii) a second message received by said storage means to simultaneously address a first number of terminal units in accordance with a first output selection signal from said comparator means when the mode field bit is in said first binary state,

(iii) a third message received by said storage means to address a second number of terminal units in response to said predetermined combination of said specified binary bits of the address field and a second output selection signal from said comparator means when the mode field bit is in a second binary state, and

(iv) a fourth message received by said storage means to address a single terminal unit in response to the first and second output selection signals from said comparator means when the mode field bit is in said second state.

2. The apparatus in accordance with claim 1 wherein said storage means comprises a shift register.

3. The apparatus in accordance with claim 1 wherein said comparator means comprises first and second groups of comparator logic elements, with a logic element in each group receiving a signal representative of a binary bit from the address portion of said storage means and an address signal from said means for generating address signals, each address signal corresponding to a binary bit of the address portion of said storage means, and each comparator logic element generating an output signal when a comparison exists between each logic element'"'"'s respective input signals, and each of said first and second groups of logic elements having a gating element associated therewith for generating said first and second output selection signals respectively when a comparison exists between all of the input signals to the comparator logic elements of the respective groups.

4. The apparatus in accordance with claim 1 wherein said gating means comprises a plurality of logic elements, a first one of said logic elements generating an output signal in response to said predetermined combination of the specified binary bits of the address field, a first pair of said logic elements, each receiving the output signal from said first one, with a one of said first pair receiving the mode field bit from said storage means and the other of said first pair receiving the second output selection signal from said comparator means, and a second pair of said plurality of logic elements each receiving the first output selection signal from said comparator means, with a one of said second pair receiving the second output selection signal and the other of said second pair receiving the mode field bit, said gating means further including a second logic element coupled to the output of each of the logic elements of said first and second pairs and responsive to output signals therefrom to selectively generate said terminal unit address enable signal.

5. Apparatus for use in each of a plurality of simultaneously addressable terminal units for recognizing addresses in messages provided thereto from an external source, each of said messages containing an address field of a specified number of binary bits, combinations of which specify terminal unit addresses, and a mode field containing at least one binary bit for specifying an address mode, said apparatus comprising:

(a) storage means for receiving a message, said storage means having an address portion and a mode portion for storing the binary bits of the message address and mode fields respectively of a received message;

(b) addressing means, said addressing means including a plurality of address assignment switches at least equal in number to the number of binary bits in the message address field in the address portion of said storage means for generating address signals in binary form representative of terminal unit addresses;

(c) comparator means, including means for combining the address signals from said addressing means and the binary bit contents of the address portion of said storage means to selectively generate at least first and second output selection signals when a comparison exists between the contents of the address portion and the address signals as assigned by said switches; and

(d) means for selectively generating a terminal unit address enable signal for addressing the respective terminal units in accordance with messages received by said storage means, said means for generating including,

(i) first gating means responsive to a predetermined combination of specified ones of the address field bits and to a first binary state of the mode field bit to simultaneously address all terminal units having a first message stored in their respective storage means,

(ii) a second gating means responsive to a first output selection signal from said comparator means and the first binary state of the mode field bit to simultaneously address a first number of terminal units having a second message in their respective storage means,

(iii) a third gating means responsive to said predetermined combination of said specified ones of the address field bits from said storage means and a second output selection signal from said comparator means to simultaneously address a second number of terminal units having a third message in their respective storage means when the mode field bit is in a second state, and

(iv) a fourth gating means responsive to the first and second output selection signals from said comparator means to address a single terminal unit having a fourth message in its respective storage means when the mode field bit is in said second state.

6. The apparatus in accordance with claim 5 wherein said storage means comprises a shift register.

7. The apparatus in accordance with claim 5 wherein the means for combining in said comparator means comprises first and second groups of comparator logic elements, with a logic element in each group receiving a signal representative of a binary bit from the address portion of said storage means and an address signal from said addressing means, each address signal corresponding to a binary bit of the address portion of said storage means, and each comparator logic element generating an output signal when a comparison exists between each logic element'"'"'s respective input signals, and each of said first and second groups of logic elements having a gating element associated therewith for generating said first and second output selection signals respectively when a comparison exists between all of the input signals to the comparator logic elements of the respective groups.

8. The apparatus in accordance with claim 5 wherein said means for selectively generating further includes a logic element coupled to the output of each of said gating means for selectively generating said terminal unit address enable signal.

9. A data communication system comprising:

(a) a message generator for generating messages, each message having an address field of a specified number of binary bits, combinations of which specify terminal unit addresses and a mode field bit containing at least one binary bit for specifying an address mode;

(b) a plurality of simultaneously addressable terminal units in communication with said message generator, each of said terminal units including,

(1) storage means for receiving messages from said message generator, said storage means having an address portion for storing the binary bits of the address and mode fields respectively of a received message,

(2) means for generating address signals representative of addresses assigned to the individual remote terminal units, the number of assignable addresses corresponding in number to at least the maximum number specifiable by the address field bits of said messages,

(3) comparator means in communication with the address portion of said storage means for generating address signals, said comparator means selectively generating at least first and second output selection signals when a comparison exists between the contents of the address portion of a received message and an assigned address specified by said address signals, and

(4) gating means responsive to specified binary bits of the address field and the mode field bit from said storage means and to said at least first and second output selection signals from said comparator means, said gating means selectively generating a terminal unit address enable signal for use by the respective terminal units in response to,

(i) a first message received by said storage means to simultaneously address all terminal units in accordance with a predetermined combination of said specified binary bits of the address field when the mode field bit is in a first binary state,

(ii) a second message received by said storage means to simultaneously address a first number of terminal units in accordance with a first output signal from said comparator means when the mode field bit is in said first binary state,

(iii) a third message received by said storage means to address a second number of terminal units in response to said predetermined combination of said specified binary bits of the address field and a second output selection signal from said comparator means when the mode field bit is in a second binary state, and

(iv) a fourth message received by said storage means to address a single terminal unit in response to the first and second output selection signals from said comparator means when the mode field bit is in said second state.

10. The data communication system in accordance with claim 9 wherein said storage means comprises a shift register.

11. The data communication system in accordance with claim 9 wherein said comparator means comprises first and second groups of comparator logic elements, with a logic element in each group receiving a signal representative of a binary bit from the address portion of said storage means and an address signal from said means for generating address signals, each address signal corresponding to a binary bit of the address portion of said storage means, and each comparator logic element generating an output signal when a comparison exists between each logic element'"'"'s respective input signals, and each of said first and second groups of logic elements having a gating element associated therewith for generating said first and second output selection signals respectively when a comparison exists between all of the input signals to the comparator logic elements of the respective groups.

12. The data communication system in accordance with claim 9 wherein said gating means comprises a plurality of logic elements, a first one of said logic elements generating an output signal in response to said predetermined combination of said specified binary bits of the address field, a first pair of said logic elements, each receiving the output signal from said first logic element, with a one of the logic elements of said first pair receiving the mode field bit from said storage means and the other logic element of said first pair receiving the second output selection signal from said comparator means, and a second pair of said plurality of logic elements, each receiving the first output selection signal from said comparator means, with a one of the logic elements of said second pair receiving the second output selection signal and the other logic element of said second pair receiving the mode field bit, said gating means further including a second logic element coupled to the output of each of the logic elements of said first and second pairs and responsive to output signals therefrom to selectively generate said terminal unit address enable signal.

13. Apparatus for use in a controllable device for recognizing addresses provided thereto in messages from an external source, each of said messages containing an address field of a specified number of binary bits, combinations of which specify addresses, and a mode field containing at least one binary bit for specifying an address mode, said apparatus comprising:

(a) storage means for receiving a message, said storage means having an address portion and a mode portion for storing the binary bits of the message address and mode fields respectively of a received message,

(b) means for generating address signals representative of addresses assigned to said controllable device, the number of assignable addresses corresponding in number to at least the maximum number specifiable by the address field binary bits of said messages;

(c) comparator means in communication with the address portion of said storage means and said means for generating address signals, said comparator means selectively generating at least first and second output selection signals when a comparison exists between the binary bit contents of the address portion and an assigned address specified by said address signals; and

(d) gating means receiving specified ones of the binary bits of the address field and the mode field bit from said storage means and said at least first and second output selection signals from said comparator means for selectively generating an address enable signal for enabling said controllable device to carry out its designed functions in response to,

(i) a first message received by said storage means, said first message having a predetermined combination of said specified ones of the binary bits in the address field and further having the mode field bit in a first binary state,

(ii) a second message received by said storage means, said second message having the mode field bit in said first binary state and effecting the generation of said first output selection signal from said comparator means in accordance with the states of the address field bits provided to said comparator means from the address portion of said storage means,

(iii) a third message received by said storage means, said third message having the mode field bit in a second binary state and effecting the generation of said second output selection signal from said comparator means as specified by said predetermined combination of said specified ones of the binary bits as provided to said comparator means from the address portion of said storage means, and

(iv) a fourth message received by said storage means, said fourth message having the mode field bit in said second state and effecting the generation of said first and second output selection signals from said comparator means in accordance with the states of the address field bits provided to said comparator means from the address portion of said storage means.

14. The apparatus in accordance with claim 13 wherein said storage means comprises a shift register.

15. The apparatus in accordance with claim 13 wherein said comparator means comprises first and second groups of comparator logic elements, with a logic element in each group receiving a signal representative of a binary bit from the address portion of said storage means and an address signal from said means for generating address signals, each address signal corresponding to a binary bit of the address portion of said storage means, and each comparator logic element generating an output signal when a comparison exists between each logic element'"'"'s respective input signals, and each of said first and second groups of logic elements having a gating element associated therewith for generating said first and second output selection signals respectively when a comparison exists between all of the input signals to the comparator logic elements of the respective groups.

16. The apparatus in accordance with claim 13 wherein said gating means comprises a plurality of logic elements, a first one of said logic elements generating an output signal in response to said predetermined combination of said specified ones of the binary bits of the address field, a first pair of said logic elements, each receiving the output signal from said first logic element, with a one of said first pair of logic elements receiving the mode field bit from said storage means and the other logic element of said first pair receiving the second output selection signal from said comparator means, and a second pair of said plurality of logic elements each receiving the first output selection signal from said comparator means, with a one of said second pair of logic elements receiving the second output selection signal and the other logic element of said second pair receiving the mode field bit, said gating means further including a second logic element coupled to the output of each of said logic elements of said first and second pairs and responsive to output signals therefrom to selectively generate said address enable signal.