Short-channel V-groove complementary MOS device
First Claim
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1. A complementary metal-oxide-semiconductor field effect device comprising:
- a lightly N-doped semiconductor substrate having a first surface and a lightly P-doped tub therein;
a first P-type region lying beneath and extending to said first surface in said semiconductor substrate;
a second P-type region lying beneath and extending to said first surface in said semiconductor substrate;
a first V-groove extending from said first surface into said semiconductor substrate lying between said first and said second P-type regions, said first V-groove having two side surfaces and two end surfaces exposing said first P-type region with a first side surface and exposing said second P-type region with a second side surface;
a first relatively thin insulating layer overlying said first V-groove;
a first N-type layer lying beneath and extending to said first surface in said substrate surrounding said first P-type region, said second P-type region and said first V-groove;
a first N-type region lying beneath and extending to said first surface in said N-doped tub;
a second N-type region lying beneath and extending to said first surface in said N-doped tub;
a second V-groove extending from said first surface into said P-doped tub disposed between said first and said second N-type regions having two side surfaces and two end surfaces;
a first P-type layer lying beneath and adjacent to a portion of said first and said second N-type regions exposed by all four surfaces of said V-groove;
a second P-type layer lying beneath and extending to said first surface in said N-type tub surrounding said first and said second N-type regions and said second V-groove;
a second relatively thin insulating layer overlying said second V-groove;
a relatively thick insulating layer of substantially uniform thickness disposed over said first surface of said semiconductor substrate having openings therein over said first and said second P-type regions, and said first and said second N-type regions;
first, second, third, and fourth electrodes respectively making electrical contact with said first, and said second P-type regions and said first and said second N-type regions; and
fifth and sixth electrodes respectively overlying said first and said second relatively thin insulating layers.
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Abstract
An improved short-channel complementary MOS transistor structure is provided. The problems of low punch-through voltage breakdown, and "short-channel effects" are particularly addressed and solved. Accurate and precise field protection of all area surrounding the channel, source and drain regions of both the p-channel MOS transistor device and the n-channel transistor device is simply and effectively accomplished. The threshold voltage of the n-channel MOS transistor device is precisely controlled by a boron implantation.
The method of manufacturing such device is disclosed.
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Citations
11 Claims
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1. A complementary metal-oxide-semiconductor field effect device comprising:
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a lightly N-doped semiconductor substrate having a first surface and a lightly P-doped tub therein; a first P-type region lying beneath and extending to said first surface in said semiconductor substrate; a second P-type region lying beneath and extending to said first surface in said semiconductor substrate; a first V-groove extending from said first surface into said semiconductor substrate lying between said first and said second P-type regions, said first V-groove having two side surfaces and two end surfaces exposing said first P-type region with a first side surface and exposing said second P-type region with a second side surface; a first relatively thin insulating layer overlying said first V-groove; a first N-type layer lying beneath and extending to said first surface in said substrate surrounding said first P-type region, said second P-type region and said first V-groove; a first N-type region lying beneath and extending to said first surface in said N-doped tub; a second N-type region lying beneath and extending to said first surface in said N-doped tub; a second V-groove extending from said first surface into said P-doped tub disposed between said first and said second N-type regions having two side surfaces and two end surfaces; a first P-type layer lying beneath and adjacent to a portion of said first and said second N-type regions exposed by all four surfaces of said V-groove; a second P-type layer lying beneath and extending to said first surface in said N-type tub surrounding said first and said second N-type regions and said second V-groove; a second relatively thin insulating layer overlying said second V-groove; a relatively thick insulating layer of substantially uniform thickness disposed over said first surface of said semiconductor substrate having openings therein over said first and said second P-type regions, and said first and said second N-type regions; first, second, third, and fourth electrodes respectively making electrical contact with said first, and said second P-type regions and said first and said second N-type regions; and fifth and sixth electrodes respectively overlying said first and said second relatively thin insulating layers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A complementary metal-oxide-semiconductor field effect device comprising:
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a. a lightly P-doped semiconductor substrate having a first surface and a lightly N-doped tub therein, b. a first P-type region lying beneath and extending to said first surface in said N-doped tub, c. a second P-type region lying beneath and extending to said first surface in said N-doped tub, d. a first V-groove extending from said first surface into said N-doped tub lying between said first and said second P-type regions, said first V-groove having two side surfaces and two end surfaces exposing said first P-type region with a first side surface and exposing said second P-type region with a second side surface, e. a first N-type layer lying beneath and extending to said first surface in said N-doped tub surrounding said first P-type region, said second P-type region, said first V-groove and said N-doped tub, f. a first relatively thin insulating layer overlying said first V-groove, g. a first electrode overlying said first relatively thin insulating layer, h. a first N-type region lying beneath and extending to said first surface in said semiconductor substrate, i. a second N-type region lying beneath and extending to said first surface in said semiconductor substrate, j. a second V-groove extending from said first surface into said semiconductor substrate disposed between said first and said second N-type regions, k. a first P-type layer lying beneath and adjacent to a portion of said first and said second N-type region in said semiconductor substrate exposed by all four surfaces of said second V-groove, l. a second P-type layer lying beneath and extending to said first surface in said semiconductor substrate surrounding said first and said second N-type regions and said second V-groove, m. a second relatively thin insulating layer overlying said second V-groove, n. a second electrode overlying said second relatively thin insulating layer, o. a relatively thick insulating layer of substantially uniform thickness disposed over said first surface of said semiconductor substrate having openings therein over said first and said second P-type regions, and said first and said second N-type regions, and p. first, second, third and fourth electrodes ov overlying said relatively thick insulating layer respectively making electrical contact with said first and said second P-type regions, and said first and said second N-type regions.
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Specification