Control apparatus including an electronic timer

• US 4,132,085 A
• Filed: 03/26/1976
• Issued: 01/02/1979
• Est. Priority Date: 06/20/1973
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Inose, Fumiyuki, Yokozawa, Norio, Fujimoto, Ryoichi, Maio, Kenji, Takasugi, Kazuo
• Primary Examiner(s): Wayner, William E.
• Assistant Examiner(s): Jones, Larry
• Application Number:
  US05/670,724
• Time in Patent Office: 1,012 Days
• Field of Search: 328/48, 328/129, 328/130, 307/293, 307/141, 307/141.4, 307/141.8, 307/117, 62/155, 62/158, 361/22
• US Class Current: 62/155
• CPC Class Codes: F25B 49/02 for compression type machines, plants or systems
• CPC Class Codes: F25D 21/006 with electronic control circuits
• CPC Class Codes: F25D 2400/24 Protection against refrigerant explosions
• CPC Class Codes: F25D 2700/12 Sensors measuring the inside temperature
• CPC Class Codes: H02H 3/0935 the timing being determined by numerical means
• CPC Class Codes: H02H 7/08 for dynamo-electric motors

Abstract

A control apparatus having an electronic timer including a plurality of flip-flop circuits connected in multiple stages in cascade. Outputs are taken from different stages of the electronic timer and the separate outputs are utilized to produce individual control timing signals which serve for controlling at least one device in accordance with the timing specific to the individual control timing signals.

Claims

1. A control apparatus comprising an electronic timer including a plurality of flip-flop circuits connected in multiple stages of first to n-th stages in cascade of that order for counting clock pulses applied to said first stages, means for taking out outputs from different stages in said electronic timer, means for producing from said outputs, separately, individual control timing signals, means for controlling at least one device by each of said control timing signals at a timing specific thereto, and means independent of the clock pulses applied to said timer for clearing the output of at least one of said different stages at a timing different of that for clearing of the output of another of said different stages.

2. A control apparatus according to claim 1, wherein said clearing means comprises means for resetting at least one flip-flop circuit relating to the output of said at least one of said different stages.

3. A control apparatus according to claim 1, wherein said clearing means comprises means for resetting at least part of the flip-flop circuits relating to the outputs of the respective different stages at timings different with each other.

4. A control apparatus according to claim 1, wherein said clearing means is responsive to a signal relating to a predetermined condition of said device.

5. A control apparatus according to claim 1, wherein said clearing means is responsive to at least one output of another of said different stages.

6. A control apparatus according to claim 1, wherein said clearing means comprises means for resetting only selected stages including said at least one stage and a part of those stages which are disposed in the cascade at orders lower than said at least one stage.

7. A control apparatus according to claim 1, in which said clearing means comprises a plurality of resetting means for resetting individually a plurality of groups of selected stages, at timings different from each other, each of said groups of selected stages including a respective one of said different stages and a part of those stages which are disposed in the cascade at orders lower than said respective one stage.

8. A control apparatus according to claim 1, wherein said clearing means is responsive to at least one output of another of said different stages and to a signal corresponding to a predetermined condition of said device for clearing the output of at least one of said different stages.

9. A control apparatus according to claim 1, wherein said clearing means includes clearing signal generating means for generating a clearing signal in response to at least one of said outputs of the different stages of said electronic timer, and supplying means for supplying said clearing signal only to at least one stage other than the stage from which said at least one output is taken out.

10. A control apparatus according to claim 9, wherein said generating means generates said clearing signal in response to at least one of said control timing signals produced from at least one of said outputs, said supplying means supplying said clearing signal to at least one flip-flop circuit only in stages other than said stage from which said at least one output producing said control timing signal to which said signal generating means is responsive is taken out.

11. A control apparatus comprising an electronic timer having a first counter to which clock pulses are applied, second and third counters to which the output of said first counter is applied, each of said first, second and third counters including a plurality of flip-flop circuits connected in multiple stages in cascade, means provided for each of said counters to take out an output from at least a selected one of the stages of each of said counters, means for producing from the outputs of the respective counters, separately, individual control timing signals, controlling means responsive to said control timing signals for controlling at least one device by each of said control timing signals at a timing specific thereto, means for generating a clearing signal in response to at least one of said outputs of said counters, and means for supplying said clearing signal only at at least one counter other than the counter from which said at least one output is taken out.

12. A control apparatus according to claim 11, wherein said clearing signal is generated in response to said at least one output from said first counter, said supplying means supplying said clearing signal only to at least one of said second and third counters for resetting the count thereof.

13. A control apparatus comprising an electronic timer including a plurality of flip-flop circuits connected in multiple stages in cascade, means for taking out outputs from different stages in said electronic timer, means for producing from said outputs, separately, individual control timing signals, means for controlling at least one device by each of said control timing signals at a timing specific thereto, means for generating a clearing signal in response to at least one of said outputs, and means for supplying said clearing signal to at least one flip-flop circuit only in stages other than the stage from which said at least one output is taken so that the stage from which said at least one output is taken is not cleared by said clearing signal.

14. A control apparatus according to claim 13, wherein said supplying means comprises means for supplying said clearing signal to all flip-flop circuits positioned in at least one of said stages other tha said stage from which said at least one output is taken out.

15. A control apparatus according to claim 13, wherein said supplying means includes means for producing a reset signal for application to said flip-flop circuits to be reset different from said flip-flop circuits having said clearing signal supplied thereto in response to said at least one output.

16. A control apparatus according to claim 13, in which each of said flip-flop circuits comprises a flip-flop of capacitance coupled type.

17. A control apparatus according to claim 13, further including means for detecting a signal corresponding to a predetermined condition of said device, said clearing signal generating means generating said clearing signal in response to both said detecting signal and said at least one output.

18. A control apparatus according to claim 13, wherein said at least one flip-flop circuit to which said clearing signal is supplied is positioned in said other stages having an order lower than said stage from which said at least one output is taken out.

19. A control apparatus according to claim 13, wherein said at least one flip-flop circuit to which said clearing signal is supplied is positioned in said other stages having an order higher than said stage from which said at least one output is taken out.

20. A control apparatus according to claim 13, wherein said generating means generates said clearing signal in response to at least one of said control timing signals produced from at least one of said outputs, said supplying means supplying said clearing signal to at least one flip-flop circuit only in stages other than said stage from which said at least one output producing said control timing signal to which said signal generating means is responsive is taken out.

21. A control apparatus comprising an electronic timer including a plurality of flip-flop circuits connected in multiple stages of first to n-th stages in cascade of that order for counting clock pulses applied to said first stages, means for taking out outputs from different stages in said electronic timer, means for producing from said outputs, separately, individual control timing signals, means for controlling at least one device by each of said control timing signals at a timing specific thereto, means for generating a reset signal in response to at least one of said outputs, and means for applying said reset signal only to at least one of said stages other than said stage from which said at least one output is taken so that the stage from which said at least one output is taken is not reset by said reset signal.

22. A control apparatus according to claim 21, wherein said means for applying a reset signal includes means for supplying said reset signals to flip-flop circuits positioned in said stages other than said stage from which said one output is taken out.

23. A control apparatus according to claim 21, wherein said means for applying a reset signal includes means for producing another reset signal for application to stages to be reset different from said stages having said reset signal applied thereto which is generated in response to said one output.

24. A control apparatus according to claim 21, further including means for detecting a signal for responding to a predetermined condition of said device, said reset signal being generated in response to said detecting signal and said one output.

25. A control apparatus according to claim 21, wherein said other stages to which said reset signal is applied are positioned at orders higher than said stage from which said output is taken out.

26. A control apparatus according to claim 21, wherein said other stages to which said reset signal is applied are positioned at orders lower than said stage from which said output is taken out.

27. A control apparatus according to claim 21, wherein said generating means generates said reset signal in response to at least one of said control timing signals produced from at least one of said outputs, said applying means applying said reset signal only to at least one of said stages other than said stage from which said at least one output producing said control timing signal to which said generating means is responsive is taken out.