Insulated gate field effect transistor having a deep channel portion more highly doped than the substrate

• US 4,132,998 A
• Filed: 08/29/1977
• Issued: 01/02/1979
• Est. Priority Date: 08/29/1977
• Status: Expired due to Term

• Current Assignee: RCA Corporation (General Electric Company)
• Original Assignee: RCA Corporation (General Electric Company)
• Inventors: Dingwall, Andrew G. F.
• Primary Examiner(s): Clawson, Jr., Joseph E.
• Application Number:
  US05/828,849
• Time in Patent Office: 491 Days
• Field of Search: 357/13, 357/23, 357/52, 357/90, 357/91
• US Class Current: 257/339
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/8605 Resistors with PN junctions

Abstract

The source and drain of an N-MOSFET can be brought closer together without substantially increasing capacitance and punch-through effects, by using a very high resistivity P-substrate, a moderately high resistivity P- type region in the channel zone and a thin but low resistivity surface-adjacent channel portion through which current flows. The P- type region and the surface-adjacent channel portion are ion-implantations. The P- type region extends deep enough into the substrate to shield the source from electrostatic coupling with the drain. Diffused, low reactance integrated circuit resistors can be made using the same principles.

Claims

1. In a very low conductivity semiconductor bulk of one type conductivity, the combination of at least two spaced terminal electrode regions of the opposite conductivity type communicating with a defined surface of the bulk, a narrow channel portion, comprising an ion-implantation, extending between the two terminal regions, and a region also extending completely between the two terminal regions, said region being located more remote from the defined surface than the channel portion and having the same conductivity as, but to a substantially greater degree than, the substrate, said region extending to a greater depth from the surface than at least one of said terminal electrode regions, but said region not extending under either of said two spaced terminal electrode regions.

2. The combination of claim 1 further comprising an insulating layer on the surface of the bulk suprajacent the first channel portion, and a gate electrode applied also suprajacent thereto and on said insulating layer.

3. The combination of claim 2 wherein the channel portion has the same conductivity type as the substrate.

4. The combination of claim 3 wherein the channel portion has P-conductivity, the terminals being of N+ type, said channel portion resulting however from an implantation of N- inducing ions.

5. The combination of claim 1 wherein said channel portion is substantially more conductive than said region.

6. An insulated gate silicon MOS device comprising

a very low conductivity substrate of one conductivity type and having a major surface;

a current carrier channel portion at the major surface;

a region of said one conductivity type located below the current carrier channel portion;

a first terminal region of the opposite conductivity type contacting one end of each of said current carrier channel portion and said region and communicating with said major surface;

a second terminal region of said opposite conductivity type, communicating with said major surface and contacting the other end of each of said current carrier channel portion and said region,

an insulating oxide layer on the major surface covering at least an area of the current carrying channel portion but leaving uncovered at least an area of the first and second terminal regions;

respective metallizings on the insulating oxide and on uncovered areas of the terminal regions to provide electrical access to the device;

said region of said one conductivity type extending deeper than, but not directly underneath, either of said terminal regions.

7. A device according to claim 6, being an enhancement N-MOS transistor.

8. A device according to claim 7 wherein both said current carrying channel portion and said region are ion-implants.