Control system capable of accommodating a plurality of momentary switching devices

• US 4,134,027 A
• Filed: 07/20/1977
• Issued: 01/09/1979
• Est. Priority Date: 07/20/1977
• Status: Expired due to Term

• Current Assignee: Emerson Electric Company
• Original Assignee: Duracell International Incorporated (Berkshire Hathaway Incorporated)
• Inventors: Small, James E., Scott, Charles E.
• Primary Examiner(s): Schaefer, Robert K.
• Assistant Examiner(s): Ginsburg, Morris
• Application Number:
  US05/817,126
• Time in Patent Office: 538 Days
• Field of Search: 307/141, 307/141.4, 307/141.8, 307/293, 361/195, 328/129, 340/309.1, 340/309.4
• US Class Current: 307/141
• CPC Class Codes: D05B 19/16 Control of workpiece movement, e.g. modulation of travel of feed dog
• CPC Class Codes: D05B 35/06 for attaching bands, ribbons, strips, or tapes or for binding
• CPC Class Codes: D05B 69/20 Control devices responsive to the number of stitches made
• CPC Class Codes: D05D 2207/02 Pneumatic or hydraulic devices
• CPC Class Codes: D05D 2303/02 Tape
• CPC Class Codes: D05D 2303/04 elastic
• CPC Class Codes: D05D 2305/12 transversally
• CPC Class Codes: D05D 2305/345 Stitch counting
• CPC Class Codes: G05B 19/07 where the programme is defined in the fixed connection of electrical elements, e.g. potentiometers, counters, transistors
• CPC Class Codes: G05B 19/108 characterised by physical layout of switches; switches co-operating with display; use of switches in a special way
• CPC Class Codes: G05B 2219/21136 Detection of zero crossing for command and maximum for reading value
• CPC Class Codes: G05B 2219/25267 Shift register

Abstract

A control system for a machine and the like having at least one cycle made up of at least two events utilizes at least one momentarily operable switching device to actuate the cycle and digital circuitry including a plurality of NAND and AND gates to implement a momentary zero potential signal produced by the switching device. The control system includes a control circuit having programming means, digital circuitry further including at least two NOR gates for latching the control circuit in various modes of operation, and timing circuitry for deriving a selectable timing period for at least one event of the cycle; and gate circuit means including additional digital circuitry for regulating at least another event of the cycle in response to the control circuit.

Claims

1. A control circuit for a machine and the like having at least one cycle made up of at least one event comprising:

at least six momentarily operable programming means each of which provides a substantially logical zero signal when momentarily closed for actuating said cycle and for selectively programming at least six time periods of said event, first gate circuit means for implementing said logical zero signal provided by said programming means, said first gate circuit means including at least six NAND gates having inputs electrically coupled to said programming means and at least three AND gates at least two of which have inputs electrically coupled to outputs of said NAND gates and at least one of which is responsive to logical states of outputs of said two AND gates, timing means responsive to logical states of said outputs of said NAND gates for timing said event in accordance with selectively programmed time periods, and function control means responsive to logical states of the output of said one AND gate of said first gate circuit means for latching said control circuit in at least one mode of operation.

2. The control circuit as recited in claim 1 wherein said first gate circuit means is responsive to the latching of said function control means.

3. The control circuit as recited in claim 2 wherein said function control means includes second gate circuit means having at least two NOR gates.

4. The control circuit as recited in claim 3 wherein one at least of said NAND gates of said first gate circuit means is latched in at least one logical state in response to said function control means.

5. The control circuit as recited in claim 4 wherein said event of said machine is activated when said NAND gate is latched in a first logical state and deactivated when said NAND gate is latched in a second logical state.

6. The control circuit as recited in claim 5 wherein some at least of said NAND gates and one at least of said AND gates of said first gate circuit means are electrically coupled to said programming means such that two at least of said AND gates are caused to make logical transitions in response to said programming means.

7. The control circuit as recited in claim 6 wherein one at least of said AND gates is caused to make a logical zero transition.

8. The control circuit as recited in claim 6 wherein said second gate circuit means of said function control means is responsive to a logical transition of one at least of said AND gates of said first gate circuit means.

9. The control circuit as recited in claim 8 wherein one at least of said NOR gates of said second gate circuit means latches in a logical state in response to said logical transition of said AND gate of said first gate circuit means whereby said control circuit is latched in said mode of operation.

10. The control circuit as recited in claim 9 wherein said NOR gate of said second gate circuit means latches in a logical one state.

11. The control circuit as recited in claim 9 wherein said NAND gate of said first gate circuit means is latched in a logical zero state in response to the latching of said NOR gate of said second gate circuit means in said logical state thereby activating said event.

12. The control circuit as recited in claim 5 wherein said function control means latches said control circuit in at least another mode of operation upon conclusion of a programmed time period.

13. The control circuit as recited in claim 12 wherein said timing means includes oscillator circuit means for generating a series of electrical pulses having a frequency variable in accordance with said selectively programmed time periods and a counter for counting a fixed number of said electrical pulses generated by said oscillator circuit means.

14. The control circuit as recited in claim 13 wherein said oscillator circuit means is activated when said NAND gate of said first gate circuit means is latched in said first logical state whereby a timing period for said event is derived.

15. The control circuit as recited in claim 14 wherein said second gate circuit means of said function control means latches in a logical state when said counter of said timing means has counted said fixed number of said electrical pulses whereby said control circuit is latched in said other mode of operation.

16. The control circuit as recited in claim 15 wherein one at least of said NOR gates of said second gate circuit means latches in a logical zero state.

17. The control circuit as recited in claim 15 wherein said NAND gate of said first gate circuit means is latched in a logical one state in response to said latching of said second gate circuit means when said counter has counted said fixed number of said electrical pulses thereby deactivating said event.

18. The control circuit as recited in claim 15 wherein said timing means is reset in response to said latching of said second gate circuit means of said function control means when said counter has counted said fixed number of said electrical pulses.

19. In a control circuit for controlling a machine and the like having at least one cycle made up of at least one event, a timing means for timing said event comprising:

oscillator circuit means for deriving at least two timing periods for said event;

said oscillator circuit means including at least one bipolar semiconductor switching device responsive to at least one electrical signal, a clock responsive to activation of said switching device for generating a series of electrical pulses, and impedance means for defining at least two selectable frequencies of said electrical pulses, said impedance means including at least two resistors and at least one patch cord whereby at least one frequency is defined by selectively electrically coupling said switching device to one of said resistors; and

a counter for counting a fixed number of said electrical pulses generated by said oscillator circuit means;

said timing periods substantially equivalent to various times required for said counter to count said fixed number of said electrical pulses.

20. The timing means as recited in claim 19 wherein said bipolar semiconductor switching device is a transistor having its base electrically coupled to said electrical signal and its collector electrically coupled to said impedance means.

21. The timing means as recited in claim 20 wherein a timing period for said event is determined by a selected frequency of said electrical pulses generated by said clock and said counter signals completion of said timing period after counting said fixed number of said pulses.

22. A control system for controlling a machine and the like having at least one cycle made up of at least two events comprising in combination:

a power supply source responsive to an alternating reference signal;

a control circuit of which only portions are responsive to an electrical signal provided by said power supply source including a plurality of momentarily operable programming means each of which is electrically coupled to ground potential whereby a substantially logical zero signal is provided for actuating said cycle when a programming means is momentarily actuated, gate circuit means for latching said control circuit in at least one mode of operation wherein a first event is activated, and timing means responsive to said latching of said gate circuit means for timing said first event of said machine in accordance with a selectively programmed time period and for signalling completion of said time period, said gate circuit means latching said control circuit in at least another mode of operation wherein said first event is deactivated; and

alarm circuit means for regulating a second event.

23. The control system as recited in claim 22 wherein said timing means include oscillator circuit means for generating a series of electrical pulses and a counter for counting a fixed number of said electrical pulses generated by said oscillator circuit means.

24. The control system as recited in claim 23 wherein said gate circuit means includes first gate circuit means for implementing said programming means and second gate circuit means responsive to implementation of said programming means by said first gate circuit means for latching said control circuit in a first mode of operation.

25. The control system as recited in claim 24 wherein said first gate circuit means is responsive to said latching of said second gate circuit means.

26. The control system as recited in claim 25 wherein said second gate circuit means is further responsive to signalling of completion of said time period by said timing means whereby said control circuit is latched in a second mode of operation.

27. The control system as recited in claim 26 wherein said first gate circuit means includes a plurality of NAND gates and a plurality of AND gates some at least of which are electrically coupled to some at least of said NAND gates.

28. The control system as recited in claim 27 wherein said second gate circuit means includes at least two NOR gates one at least of which is electrically coupled to said first gate circuit means and one at least of which is electrically coupled to said timing means.

29. The control system as recited in claim 28 wherein one at least of said NAND gates of said first gate circuit means is latched in at least one logical state in response said latching of to said second gate circuit means.

30. The control system as recited in claim 29 wherein one at least of said events is activated when said NAND gate of said first gate circuit means is latched in a first logical state and deactivated when said NAND gate is latched in a second logical state.

31. The control system as recited in claim 23 wherein said alarm circuit means is actuated in response to a signal provided by said timing means indicating completion of said time period of said first event.

32. The control system as recited in claim 31 wherein said alarm circuit means includes at least two NOR gates one at least of which is electrically coupled to said timing means.

33. The control system as recited in claim 32 wherein one at least of said NOR gates of said alarm circuit means is caused to make a logical transition when said counter of said timing means has counted said fixed number of said electrical pulses thereby activating said second event of said machine.

34. The control system as recited in claim 33 wherein said logical transition of said NOR gate causes another one of said NOR gates to make a logical transition thereby deactivating said second event of said machine.

35. The control system as recited in claim 34 wherein said logical transition of said other NOR gate is delayed such that a timing period for said second event is thereby derived.

36. The control system as recited in claim 35 further including power circuit means responsive to a machine condition for establishing at least one mode of operation of said control circuit whereby said cycle of said control system is truncated.

37. The control system as recited in claim 36 further including indicating means responsive to actuation of said timing means for indicating execution of said cycle.

38. A control system for controlling a machine and the like having at least one cycle made up of at least one event which includes at least two subevents comprising in combination:

a power supply source responsive to an alternating reference signal;

a control circuit of which only portions are responsive to an electrical signal provided by said power supply source including a plurality of momentarily operable programming means each of which is electrically coupled to ground potential whereby a substantially logical zero signal is provided for actuating said cycle when a programming means is momentarily actuated, gate circuit means for latching said control circuit in at least one mode of operation wherein said event is activated, and timing means responsive to said latching of said gate circuit means for timing said event of said machine in accordance with a selectively programmed time period and for signalling completion of said time period, said gate circuit means latching said control circuit in at least another mode of operation wherein said event is deactivated; and

delay timing means electrically coupled to said timing means for administering a sequential activation and deactivation of said two subevents in response to initiation and completion of said time period.

39. The control system as recited in claim 38 wherein said timing means includes oscillator circuit means for generating a series of electrical pulses and a counter for counting a fixed number of said electrical pulses generated by said oscillator circuit means.

40. The control system as recited in claim 39 further including switching means responsive to initiation and completion of said time period for activating and deactivating a first subevent of said event.

41. The control system as recited in claim 40 wherein said delay timing means in response to initiation of said time period delays activation of a second subevent of said event for a predetermined time period after activation of said first subevent.

42. The control system as recited in claim 41 wherein said oscillator circuit means includes a first switching means responsive to said latching of said gate circuit means and said delay timing means and a second switching means are responsive to actuation of said first switching means.

43. The control system as recited in claim 42 wherein said delay timing means includes at least one capacitance means and a timing circuit.

44. The control system as recited in claim 43 wherein said activation of said second subevent is delayed for a period determined by a time required to substantially charge said capacitance means.

45. The control system as recited in claim 44 wherein said second switching means is electrically coupled to said delay timing means whereby deactivation of said first subevent is delayed.

46. The control system as recited in claim 45 wherein deactivation of said first subevent is delayed for a period determined by a time required for said capacitance means to substantially discharge.