Absolute resolver angle to digital converter circuit

• US 4,134,106 A
• Filed: 12/16/1976
• Issued: 01/09/1979
• Est. Priority Date: 12/16/1976
• Status: Expired due to Term

• Current Assignee: The Bendix Corporation (Honeywell International Inc.)
• Original Assignee: The Bendix Corporation (Honeywell International Inc.)
• Inventors: Hungerford, William R.
• Primary Examiner(s): Sloyan, Thomas J.
• Application Number:
  US05/751,414
• Time in Patent Office: 754 Days
• Field of Search: 340/347 M, 340/347 SY, 340/347 AD, 340/198, 318/661, 318/569, 235/92 MP
• US Class Current: 341/116
• CPC Class Codes: H03M 1/485 for position encoding, e.g. using resolvers or synchros

Abstract

An absolute resolver digitizer for a numerical control system generating a digital number indicative of the absolute angular position of a resolver'"'"'s rotor within a given revolution is disclosed herein. The resolver digitizer comprises a reference generator generating resolver excitation signals and a digital number indicative of the phase of the generated excitation signals and a resolver follower generating a digital number indicative of the sum of phase of the excitation signal generated by the reference generator and the angular position of the resolver'"'"'s rotor. Subtraction of the digital number generated by the reference generator from the digital number generated by the resolver follower produces a digital number indicative of the resolver'"'"'s absolute position within a given revolution. This subtraction may be performed by a separate circuit within the absolute resolver digitizer or may be performed by the computer associated with the numerical control system.

Claims

1. An absolute resolver digitizer for use in combination with a resolver having stator means and a rotor means comprising:

reference generator means for generating resolver excitation signals exciting the resolver'"'"'s stator means to generate a rotating field and for generating digital field position data indicative of the instantaneous angular position of said ratating field; and

resolver follower means for generating digital sum position data indicative of the sum of the instantaneous position of the resolver'"'"'s rotor means in response to signals induced in the rotor means by said rotating field;

wherein said reference generator means comprises

reference generator counter means for storing counts at a predetermined frequency and for generating an overflow signal when the stored counts reach a predetermined number wherein the number of counts stored in said reference generator counter means is said field position data; and

resolver exciter means for generating said resolver excitation signals in response to said overflow signals; and

wherein said resolver follower means comprises

phrase modulator means for generating phase modulated signals and said digital sum data in response to correction signals;

phase comparator means for comparing the phase of the signals induced in said rotor means with said phase modulated signals to generate error signals indicative of the phase error between the two signals compared; and

correction circuit means for generating said correction signals in response to said error signals.

2. The absolute resolver digitizer of claim 1 further including circuit means for generating digital data indicative of the resolver'"'"'s rotor means instantaneous angular position in response to said field position data and said sum position data.

3. The absolute resolver digitizer of claim wherein the error signals generated by said phase comparator means comprises a phase error signal indicative of the magnitude of the phase error between the signal induced in said rotor means and said phase modulted signal and a sign signal indicative of which compared signal was first received, said correction circuits means comprises:

integrator means for integrating said phase error signals and said sign signals to generate pulse signals at a rate indicative of the average angular velocity of said rotor means and an integrated sign signal indicative of the direction in which said rotor means is moving;

sign logic means receiving said phase error signal and said integrated sign signal for terminating the transmission of the integrated sign signal when the phase comparator is generating said error signal;

a first summation circuit combining said phase error signal with the pulse signals generated by said integrator means to generate a correction pulse signal; and

a second summation circuit combining said sign signal with the integrated sign signal transmitted by said sign logic means to generate a correction sign signal.

4. The absolute resolver digitizer of claim 3 wherein said phase error signal is a phase error pulse signal having a pulse duration indicative of the magnitude of the phase error between the signal induced in said rotor means and said phase modulated signal, said integrator comprises:

up/down counter means, enabled by said phase error pulse signal and counting in a direction determined by said sign signal for storing an integrated number of counts indicative of the integrated duration of successive phase error signals and for generating said integrated sign signal indicative of whether the integrated number of counts are greater or less than zero; and

a rate multiplier for generating said pulse signals at a rate proportional to the number of integrated counts stored in said up/down counter means.

5. The absolute resolver digitizer of claim 3 wherein said phase modulator means comprises:

a counter enable circuit for generating counter enable signals in response to said correction pulse signals and said correction sign signal, said counter enable circuit generating pulse counter enable signals at said predetermined frequency in response to the absence of said correction pulse signals, generating a continuous counter enable signal in response to the simultaneous occurrence of a correction pulse signal and a correction sign signal and generating no counter enable signal in response to the occurrence of a correction pulse signal and the absence of a correction sign signal; and

a phase modulator counter for storing a number of counts in response to said counter enable signals, said phase modulator counter storing counts at said predetermined frequency in response to counter enable signals in the form of pulses at said predetermined frequency, storing counts at twice said predetermined frequency in response to a continuous counter enable signal, and storing no counts in the absence of a counter enable signal;

wherein the instantaneous number of counts stored in said phase modulator counter is said digital sum position data and the overflow signal indicative of said predetermined number of stored counts is said phase modulated signal transmitted to said comparator means.

6. The absolute resolver digitizer of claim 5 wherein said counter enable circuit comprises:

a pulse generating circuit generating said pulse counter enable signals at said predetermined frequency; and

a gate circuit receiving said correction pulse signals, said correction sign signals and pulse counter enable signals, said gate circuit transmitting said pulse counter enable signals in response to an absence of a correction pulse signal, transmitting said correction pulse signals in response to the simultaneous occurrence of a correction sign signal, and blocking the transmission of all signals in response to the occurrence of a correction pulse signal and the absence of a correction sign signal.

7. The absolute resolver digitizer of claim 5 further including circuit means for generating digital data indicative of the resolver'"'"'s rotor means instantaneous position in response to the number of counts stored in said reference generator counter means and said phase modulator counter.

8. An apparatus for generating a digital signal indicative of an angular displacement comprising:

a resolver having stator means for generating a field and rotor means responsive to an angular displacement for generating an induced signal indicative of the angular displacement between said field and said rotor means;

reference generator means for generating resolver excitation signals exciting said stator means to generate a rotating field and for generating digital field position data indicative of the instantaneous angular position of said rotating field; and

resolver follower means for generating digital sum position data indicative of the sum of the instantaneous angular position of said rotating field and the instantaneous position of said rotor means in response to signals induced in said rotor means by said rotating field;

wherein said reference generator means comprises

reference generator counter means for storing counts at a predetermined frequency and for generating an overflow signal when the stored counts reach a predetermined number wherein the number of counts stored in said reference generator counter means is said field position data; and

resolver exciter means for generating said resolver excitation signals in response to said overflow signals; and

wherein said resolver follower means comprises

phase modulator means for generating phase modulated signals and said digital sum data in response to correction signals;

phase comparator means for comparing the phase of the signals induced in said rotor means with said phase modulated signals to generate error signals indicative of the phase error between the two signals compared; and

correction circuit means for generating said correction signals in response to said error signals.

9. The apparatus digitizer of claim 8 further including circuit means for generating digital data indicative of said rotor means instantaneous angular position in response to said field position data and said sum position data.

10. The apparatus digitizer of claim 8 wherein the error signals generated by said phase comparator means comprises a phase error signal indicative of the magnitude of the phase error between the signal induced in said rotor means and said phase modulated signal and a sign signal indicative of which compared signal was first received, said correction circuit means comprises:

integrator means for integrating said phase error signals and said sign signals to generate pulse signals at a rate indicative of the average angular velocity of said rotor means and an integrated sign signal indicative of the direction in which said rotor means is moving;

sign logic means receiving said phase error signal and said integrated sign signal for terminating the transmission of the integrated sign signal when the phase comparator is generating said error signal;

a first summation circuit combining said phase error signal with the pulse signals generated by said integrator means to generate a correction pulse signal; and

a second summation circuit combining said sign signal with the integrated sign signal transmitted by said sign logic means to generate a correction sign signal.

11. The apparatus digitizer of claim 10 wherein said phase error signal is a phase error pulse signal having a pulse duration indicative of the magnitude of the phase error between the signal induced in said rotor means and said phase modulated signal, said integrator comprises:

up/down counter means, enabled by said phase error pulse signal and counting in a direction determined by said sign signal for storing an integrated number of counts indicative of the integrated duration of successive phase error pulse signals and for generating said integrated sign signal indicative of whether the integrated number of counts are greater or less than zero; and

a rate multiplier for generating said pulse signals at a rate proportional to the number of integrated counts stored in said up/down counter means.

12. The apparatus digitizer of claim 10 wherein said phase modulator means comprises:

a counter enable circuit for generating counter enable signals in response to said correction pulse signals and said correction sign signal, said counter enable circuit generating pulse counter enable signals at said pedetermined frequency in response to the absence of said correction pulse signals, generating a continuous counter enable signal in response to the simultaneous occurrence of a correction pulse signal and a correction sign signal and generating no counter enable signal in response to the occurrence of a correction pulse signal and the absence of a correction sign signal; and

a phase modulator counter for storing a number of counts in response to said counter enable signals, said phase modulator counter storing counts at said predetermined frequency in response to counter enable signals in the form of pulses at said predetermined frequency, storing counts at twice said predetermined frequency in response to a continuous counter enable signal, and storing no counts in the absence of a counter enable signal;

wherein the instantaneous number of counts stored in said phase modulator counter is said digital sum position data and the overflow signal indicative of said predetermined number of stored counts is said phase modulated signal transmitted to said comparator means.

13. The apparatus digitizer of claim 12 wherein said counter enable circuit comprises:

a pulse generating circuit generating said pulse counter enable signals at said predetermined frequency; and

a gate circuit receiving said correction pulse signals, said correction sign signals and pulse counter enable signals, said gate circuit transmitting said pulse counter enable signals in response to an absence of a correction pulse signal, transmitting said correction pulse signals in response to the simultaneous occurrence of a correction sign signal, and blocking the transmission of all signals in response to the occurrence of a correction pulse signal and the absence of a correction sign signal.

14. The apparatus digitizer of claim 12 further including circuit means for generating digital data indicative of the resolver'"'"'s rotor means instantaneous position in response to the number of counts stored in said reference generator counter means and said phase modulator counter.

15. In combination with a numerical control system for controlling the displacement of a moveable member along at least one axis, said numerical control system comprising:

a moveable member operable to move in response to command signals;

a resolver having stator means for generating a field and rotor means angularly displaced with the movement of said moveable member, for generating a phase signal indicative of the position of said moveable member, said phase signal being indicative of the phase angle between a field generated by said stator means and the angular position of said rotor means;

means for reading data from a permanent recording to generate input data indicative of the desired movement of said moveable member; and

computer means having storage and computation capabilities for generating commanded position data indicative of the desired position of said moveable member in response to said input date and for generating said command signal in response to the difference between said commanded position data and actual position data indicative of the instantaneous actual position of the moveable member

an improvement for generating the actual position data comprising

reference generator means for generating signals exciting the resolver'"'"'s stator means to generate a rotating field and for generating digital field position data indicative of the instantaneous angular orientation of said rotating field; and

resolver follower means for generating digital sum position data indicative of the instantaneous angular position of said rotating field and the instantaneous position of the resolver'"'"'s rotor means in response to signals induced in the rotor means by said rotating field wherein the difference between said sum position data and said field position data is actual position data indicative of the instantaneous position of said rotor means;

wherein said reference generator means comprises

reference generator counter means for storing counts at a predetermined frequency and for generating an overflow signal when the stored counts reach a predetermined number wherein the number of counts stored in said reference generator counter means is said field position data; and

resolver exciter means for generating said resolver excitation signals in response to said overflow signals; and

wherein said resolver follower means comprises

phase modulator means for generating phase modulated signals and said digital sum data in response to correction signals;

phase comparator means for comparing the phase of the signals induced in said rotor means with said phase modulated signals to generate error signals indicative of the phase error between the two signals compared; and

correction circuit means for generating said correction signals in response to said error signals.

16. The combination of claim 15 wherein said absolute resolver digitizer further includes circuit means for combining said field position data with said sum position data to generate said actual position data.

17. The combination of claim 15 wherein said computer means includes means for combining said sum position data and said field position data to generate said actual position data, said sum position data and field position data are input directly to said computer means.

18. The combination of claim 15 wherein the error signals generated by said phase comparator means comprises a phase error signal indicative of the magnitude of the phase error between the signal induced in said rotor means and said phase modulated signal and a sign signal indicative of which compared signal was first received, said correction circuit means comprises:

integrator means for integrating said phase error signals and said sign signals to generate pulse signals at a rate indicative of the average angular velocity of said rotor means and an integrated sign signal indicative of the direction in which said rotor means is moving;

sign logic means receiving said phase error signal and said integrated sign signal for terminating the transmission of the integrated sign signal when the phase comparator is generating said error signal;

a first summation circuit combining said phase error signal with the pulse signals generated by said integrator means to generate a correction pulse signal; and

a second summation circuit combining said sign signal with the integrated sign signal transmitted by said sign logic means to generate a correction sign signal.

19. The combination of claim 18 wherein said phase error signal is a phase error pulse signal having a pulse duration indicative of the magnitude of the phase error between the signal induced in said rotor means and said phase modulated signal, said integrator comprises:

up/down counter means, enabled by said phase error pulse signal and counting in a direction determined by said sign signal for storing an integrated number of counts indicative of the integrated duration of successive phase error pulse signals and for generating said integrated sign signal indicative of whether the integrated number of counts are greater or less than zero; and

a rate multiplier for generating said pulse signals at a rate proportional to the number of integrated counts stored in said up/down counter means.

20. The combination of claim 18 wherein said phase modulator means comprises:

a counter enable circuit for generating counter enable signals in response to said correction pulse signals and said correction sign signal, said counter enable circuit generating pulse counter enable signals at said predetermined frequency in response to the absence of said correction pulse signals, generating a continuous counter enable signal in response to the simultaneous occurrence of a correction pulse signal and a correction sign signal and generating no counter enable signal in response to the occurrence of a correction pulse signal and the absence of a correction sign signal; and

a phase modulator counter for storing a number of counts in response to said counter enable signals, said phase modulator counter storing counts at said predetermined frequency in response to counter enable signals in the form of pulses at said predetermined frequency, storing counts at twice said predetermined frequency in response to a continuous counter enable signal, and storing no counts in the absence of a counter enable signal;

wherein the instantaneous number of counts stored in said phase modulator counter is said digital sum position data and the overflow signal indicative of said predetermined number of stored counts is said phase modulated signal transmitted to said comparator means.

21. The combination of claim 20 wherein said counter enable circuit comprises:

a pulse generating circuit generating said pulse counter enable signals at said predetermined frequency; and

a gate circuit receiving said correction pulse signals, said correction sign signals and pulse counter enable signals, said gate circuit transmitting said pulse counter enable signals in response to an absence of a correction pulse signal, transmitting said correction pulse signals in response to the simultaneous occurrence of a correction sign signal, and blocking the transmission of all signals in response to the occurrence of a correction pulse signal and the absence of a correction sign signal.

22. The absolute resolver digitizer of claim 20 further including circuit means for generating digital data indicative of the resolver'"'"'s rotor means instantaneous position in response to the number of counts stored in said reference generator counter means and said phase modulator counter.