Data acquisition from multiple sources
First Claim
1. A data acquisition system having a plurality of transducers whose outputs are to be acquired, comprising:
- a plurality of independently and parallelly operating commutators each connected to and cyclically interrogating some of the transducers of the plurality in independent cycles and each providing an unbuffered PCM signal train, there being a plurality of independent and parallel PCM signal trains accordingly;
A plurality of decommutators connected for respectively receiving the signal trains and respctively operating in synchronism with the respective commutator cycles for separating the signals in accordance with their respective transducer origin;
a plurality of independently addressible buffer means respectively connected to the decommutators for storing the separated signals as data in individually addressible locations;
means included in each buffer means for accessing the locations in synchronism with the decommutation cycles;
a common data bus connected to all of the buffer means of the plurality of buffer means; and
a plurality of independently operating processors connected to the bus, each having independent access to all said buffer means of the plurality to extract therefrom the signals as stored for processing.
0 Assignments
0 Petitions
Accused Products
Abstract
A data acquisition system includes groups of transducers, a separate commutator for each group cyclically interrogates the transducers of the group. The resulting signal trains are separately decommutated and the data from each transducer group are stored in separate buffer systems. Each buffer system has a pair of buffers which alternate between reading and writing and a mask control selectively causes updating of the buffer content or copying from one into the other. A third buffer in each system is continuously updated. A formatting processor calls on all buffer pairs to assemble a PCM signal train in which the data from each transducer occur at least once in a cyclically repeated main frame. Buffer locations more frequently updated are called on more than once in the main frame. This processor is programmed to assemble the buffer addresses by counting up from starting addresses for a ROM that holds each buffer address once. Separate processors use the content of continuously updated buffers to close feedback loops.
47 Citations
18 Claims
-
1. A data acquisition system having a plurality of transducers whose outputs are to be acquired, comprising:
-
a plurality of independently and parallelly operating commutators each connected to and cyclically interrogating some of the transducers of the plurality in independent cycles and each providing an unbuffered PCM signal train, there being a plurality of independent and parallel PCM signal trains accordingly; A plurality of decommutators connected for respectively receiving the signal trains and respctively operating in synchronism with the respective commutator cycles for separating the signals in accordance with their respective transducer origin; a plurality of independently addressible buffer means respectively connected to the decommutators for storing the separated signals as data in individually addressible locations; means included in each buffer means for accessing the locations in synchronism with the decommutation cycles; a common data bus connected to all of the buffer means of the plurality of buffer means; and a plurality of independently operating processors connected to the bus, each having independent access to all said buffer means of the plurality to extract therefrom the signals as stored for processing. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A data acquisition system having a plurality of transducers whose outputs are to be acquired, comprising:
-
a plurality of independently and parallelly operating commutators, each being connected to and cyclically interrogating some of the transducers of the plurality in idependent cycles and providing an unbuffered PCM signal train, there being a plurality of independent parallel PCM signal trains accordningly; a plurality of decommutators connected for respectively receiving the signal trains of the plurality for separating the signals in accordance with their respective transducer origin so that for each commutation cycle there is a corresponding decommutation cycle in which separated signals from each transducer connected to the respectively associated commutator appear, once per cycle; a plurality of independently addressible buffer means respectively connected to the decommutators for storing the separated signals as data in individually addressable locations, the same location being updated as to its data content upon being addressed in sequential cycles to receive the separated signals as new data from the respective decommutators or otherwise; means included in each of the buffer means for selectively controlling the updating of the storage locations in the buffer means, so that some of the locations receive new data from the respective decommutator less frequently than once per commutator-decommutator cycle; and a processor having access to all said buffer means for providing a sequence of buffer addresses for extracting from the buffer means of the plurality data as stored, independently from the commutation cycles, and assembling the data as sequentially extracted to provide a stream of data within a main frame, being repeated on a cyclic basis wherein data within a main frame, having originated in some of the transducers appear more than once in such a main frame, data having originated in other ones of the transducers appearing only once in the main frame, the buffer locations storing the signals from said other transducers having been updated less frequently by operation of said means for selectively controlling. - View Dependent Claims (12, 13, 14, 15, 16)
-
-
17. A data acquisition system having a plurality of transducers whose outputs are to be acquired, comprising:
-
a plurality of independently and parallelly operating commutators each connected to and cyclically interrogating some of the transducers of the plurality in independent cycles and each providing an unbuffered PCM signal train, there being a plurality of independent and parallel PCM signal trains accordingly; a plurality of decommutators connected for respectively receiving the signal trains and respectively operating in synchronism with the respective commutation cycle for separating the signals in accordance with their respective transducer origin; a plurality of independently addressible buffer means respectively connected to the decommutators for storing the separated signals as data in individually addressible locations; a data bus connected to all of said buffer means of the plurality of buffer means; and a processor providing a particular sequence of address signals for all said buffer means, each of said address signals being effective in but one of the buffer means to extract from the respectively accessed location data stored therein so that pursuant to the sequence of address signals data are assembled in a data stream on said bus. - View Dependent Claims (18)
-
Specification