Data transfer control system

• US 4,138,732 A
• Filed: 10/27/1976
• Issued: 02/06/1979
• Est. Priority Date: 10/31/1975
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Electric Co., Ltd. (Toshiba Corporation)
• Original Assignee: Tokyo Shibaura Electric Co., Ltd. (Toshiba Corporation)
• Inventors: Suzuki, Seigo, Uemori, Keiji
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Heckler, Thomas M.
• Application Number:
  US05/735,961
• Time in Patent Office: 832 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 365/80, 365/81
• US Class Current: 710/31
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence
• CPC Class Codes: G06F 7/785 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using a RAM

Abstract

A data transfer control system for controlling data transfer between a processor and an input/output device comprises a multi-layer stack for temporarily storing transfer data, such as a first-in first-out stack or a last-in first-out stack; first and second up/down counters having a preset function and permitting any designated address at the stack to be varied; and first and second pointer registers for storing any initially designated address data which is stored in the counter. The first counter permits a direction of a count operation to be determined by the processor and the first point register has an initially designated address data stored therein by the processor. The second counter permits a direction of a count operation to be determined by the input/output device and the second point register has an initially designated address data stored therein by the input/output device. The direction of a data flow at the stack is varied dependent upon the direction in which the first and second counters effect count operations.

Claims

1. In combination with a data transfer control system for controlling a data transfer between a processor and an input/output device including

a stack which is addressable and which is disposed between the processor and the input/output device to permit data supplied from the processor and input/output device to be temporarily stored in the stack;

a first register for storing an initial address and final address from the processor;

a first up/down counter connected to the first register, said first register adapted to load said initial address and said final address in said first counter;

a clock pulse generator for sequentially supplying first clock signals to said first up/down counter, whereby said first up/down counter begins a count-up or count-down operation in response to a count-up or count-down control signal applied from the processor and, during the count-up or count-down operation, delivers an output signal for each sequential first clock signal for designating an address of the stack; and

a first address decoder connected to the first counter for decoding each output signal of the first counter and designating the corresponding address at the stack;

the improvement providing bidirectional transfer of information through the stack comprising;

a second register for storing an initial address and final address from the input/output device;

a second up/down counter connected to the second register, said second register adapted to load said initial address and final address from the input/output device in said second counter, said clock pulse generator sequentially applying second clock signals to said second up/down counter, whereby said second up/down counter begins a count-up or count-down operation in response to a count-up or count-down control signal applied from the input/output device and, during the count-up or count-down operation, delivers an output signal for each sequential second clock signal for designating an address of the stack; and

a second address decoder connected to the second counter for decoding each output signal of the second counter and designating the corresponding address at the stack.

2. In combination with a data transfer control system for controlling a data transfer between a first processor and a second processor including

a stack which is addressable and which is disposed between the first and second processors to permit data supplied from the first processor and second processor to be temporarily stored in the stack;

a first register for storing an initial address and final address from the first processor;

a first up/down counter connected to the first register, said final register adapted to load said initial address and said final address in said first counter;

a clock pulse generator for sequentially supplying first clock signals to said first up/down counter, whereby said first up/down counter begins a count-up or count-down operation in response to a count-up or count-down control signal applied from the first processor and, during the count-up or count-down operation, delivers an output signal for each sequential first clock signal for designating an address of the stack; and

a first address decoder connected to the first counter for decoding each output signal of the first counter and designating the corresponding address at the stack;

the improvement providing bidirectional transfer of information through the stack comprising;

a second register for storing an initial address and final address from the second processor;

a second up/down counter connected to the second register, said second register adapted to load the initial address and final address from the second processor in said counter, said clock pulse generator sequentially applying second clock signals to said second up/down counter, whereby said second up/down counter begins a count-up or count-down operation in response to a count-up or count-down control signal applied from the second processor and, during the count-up or count-down operation, delivers an output signal for each sequential second clock signal for designating an address of the stack; and

a second address decoder connected to the second counter for decoding each output signal of the second counter and designating the corresponding address at the stack.

3. In combination with a data transfer control system for controlling a data transfer between a processor and an input/output device including

a stack which is addressable and which is disposed between the processor and the input/output device to permit data supplied from the processor and input/output device to be temporarily stored in the stack;

a first register for storing an initial address and final address from the processor;

a first up/down counter connected to the first register, said first register adapted to load said initial address and final address in the first up/down counter;

a clock pulse generator for sequentially supplying first clock signals to said first up/down counter, whereby said first up/down counter is set to its count-up or count-down operation in response to a count-up or count-down control signal applied from the processor, and wherein said first counter, to which said initial and final addresses are loaded therein, is adapted to count first clock signals sequentially supplied from the clock pulse generator so that the contents of the first counter are changed from the contents corresponding to said initial address up to the contents corresponding to said final address, and wherein said first up/down counter delivers an output signal for each of the first clock signals for designating an address of the stack; and

a first address decoder connected to the first counter to decode each output signal of the first counter so as to designate the corresponding address at said stack;

the improvement providing bidirectional transfer of information through the stack comprising;

a second register for storing an initial address and final address from the input-output device;

a second up/down counter, connected to the second register, said second register adapted to load said initial address and final address from the input/output device in the second up/down counter, whereby said second up/down counter is set to its count-up or count-down operation in response to a count-up or count-down control signal applied from the input/output device, and wherein said second counter, after said initial and final addresses from the input/output device are loaded therein, is adapted to count second clock signals sequentially supplied from the clock pulse generator so that the contents of the second counter are changed from the contents corresponding to said initial address up to the contents corresponding to said final address, and wherein said second up/down counter delivers an output signal for each count of the second clock signal for designating an address of the stack; and

a second address decoder connected to the second counter to decode each output signal of the second counter so as to designate the corresponding address at said stack.

4. In combination with a data transfer control system for controlling a data transfer between a first processor and a second processor including

a stack which is addressable and which is disposed between the first and second processors to permit data supplied from the first and second processors to be temporarily stored in the stack;

a first register for storing an initial address and final address from the first processor;

a first up/down counter connected to the first register, said first register being adapted to load said initial address and final address in the first up/down counter;

a clock pulse generator for sequentially supplying first clock signals to said first up/down counter, whereby said first up/down counter is set to its count-up or count-down operation in response to a count-up or count-down control signal applied from the first processor, and wherein said first counter, after said initial and final addresses are loaded therein, is adapted to count first clock signals sequentially supplied from the clock pulse generator so that the contents of the first counter are changed from the contents corresponding to said initial address up to the contents corresponding to said final address, and wherein said first up/down counter delivers an output signal for each of the first clock signals for designating an address of the stack; and

a first address decoder connected to the first counter to decode each output signal of the first counter so as to designate the corresponding address at said stack;

the improvement providing bidirectional transfer of information through the stack comprising;

a second register for storing an initial address and final address from the second processor;

a second up/down counter connected to the second register, said second register adapted to load said initial address and final address from the second processor in the second up/down counter, whereby said second up/down counter is set to its count-up or count-down operation in response to a count-up or count-down control signal applied from the second processor, and wherein said second counter, after said initial and final addresses from the second processor are loaded therein, is adapted to count second clock signals sequentially supplied from the clock pulse generator so that the contents of the second counter are changed from the contents corresponding to said initial address up to the contents corresponding to said final address, and wherein said second up/down counter delivers an output signal for each of the second clock signals for designating an address of the stack; and

a second address decoder connected to the second counter to decode each output signal of the second counter so as to designate the corresponding address at said stack.