Time division multiplex transmission system in which electrical power is transmitted to remote terminals from a central unit simultaneously with address and control signals

• US 4,139,737 A
• Filed: 09/01/1977
• Issued: 02/13/1979
• Est. Priority Date: 09/10/1976
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Asahi Matsushita Electric Works Ltd. (Panasonic Holdings Corporation)
• Inventors: Shimada, Isao, Akiba, Osamu
• Primary Examiner(s): Cooper, William C.
• Assistant Examiner(s): Popek, Joseph A.
• Application Number:
  US05/829,885
• Time in Patent Office: 530 Days
• Field of Search: 179/15 AL, 179/2 AM, 340/151, 340/183, 340/203
• US Class Current: 370/449
• CPC Class Codes: H04J 3/245 in which the allocation protocols between more than two stations share the same transmission medium stations for satellite systems H04B7/185
• CPC Class Codes: H04Q 9/14 Calling by using pulses

Abstract

A time division multiplex transmission system including a central unit and a plurality of terminal units connected through a single pair of bus lines to the central unit. The central unit transmits at least a set of address and control signals sequentially to the respective terminal units and also an electric power required for operating and controlling the respective terminal units at least accompanying the address and control signals. The respective terminal units include a condenser for accumulating the electric power from the central unit so that each terminal unit corresponding to each address signal from the central unit performs any desired operation with the accumulated power and transmits a response signal depending on a result of the operation to the central unit responsive to the control signal.

Claims

1. In a time division multiplex transmission system including a central unit and a plurality of terminal units, said central unit transmitting at least address signals and control signals respectively in a set sequentially to respective ones of said terminal units, each of said terminal units responding to a corresponding address signal which accompanies each control signal and receiving said control signal to be thereby controlled and transmitting to the central unit a response signal in accordance with the control signal, and said address, control and response signals being arranged as time-divided in a series time band;

an arrangement in which said terminal units are respectively provided with means for accumulating therein an electric power required for operating the terminal unit and supplying said accumulated power to the terminal unit, said electrical power being transmitted from the central unit accompanying at least the address and control signals, wherein a direct current voltage higher than a required voltage for each terminal unit is transmitted from the central unit as superposed at least on the address and control signals and at least during the period of transmitting the signals.

2. In a time division multiplex transmission system including a central unit and a plurality of terminal units, said central unit transmitting at least address signals and control signals respectively in a set sequentially to respective ones of said terminal units, each of said terminal units responding to a corresponding address signal which accompanies each control signal and receiving said control signal to be thereby controlled and transmitting to the central unit a response signal in accordance with the control signal, and said address, control and response signals being arranged as time-divided in a series time band;

an arrangement in which said terminal units are respectively provided with means for accumulating therein an electric power required for operating the terminal unit and supplying said accumulated power to the terminal unit, said electric power being transmitted from the central unit accompanying at least the address and control signals, wherein a predetermined voltage signal is transmitted from the central unit to a respective terminal unit also during transmissions of the response signals from the respective terminal units, the response signal is transmitted in the form of a current signal by short-circuiting and opening a circuit of the respective terminal units, and said electric power accumulating means accumulates the power also during transmissions of the response signals.

3. In a time division multiplex transmission system including a central unit and a plurality of terminal units, said central unit transmitting at least address signals and control signals respectively in a set sequentially to respective ones of said terminal units, each of said terminal units reponding to a corresponding address signal which accompanies each control signal and receiving said control signal to be thereby controlled and transmitting to the central unit a response signal in accordance with the control signal, and said address, control and response signals being arranged as time-divided in a series time band;

an arrangement in which said terminal units are respectively provided with means for accumulating therein an electric power required for operating the terminal unit and supplying accumulated power to the terminal unit, said electric power being transmitted from the central unit accompanying at least the address and control signals, wherein a direct current voltage higher than a required voltage for each terminal unit is transmitted from the central unit as superposed at least on the address and control signals and at least during the period of transmitting the signals, further wherein a predetermined voltage signal is transmitted from the central unit to the terminal unit also during the transmission of the response signal from the respective terminal units, the response signal is transmitted in the form of a current signal by short-circuiting and opening a circuit of the respective terminal units, and said electric power accumulating means accumulates the power also during transmissions of the response signals.

4. In a time division multiplex transmission system including a central unit and a plurality of terminal units, said central unit transmitting at least address signals and control signals respectively in a set sequentially to respective ones of said terminal units, each of said terminal units which corresponds to each address signal which accompanies each control signal receiving said control signal to be thereby controlled and transmitting to the central unit a response signal in accordance with the control signal, and said address, control and response signals being arranged as time-divided in a series time band;

an arrangement in which said terminal units are respectively provided with means for accumulating therein an electric power required for operating the terminal unit and supplying said power accumulated to the terminal unit, said electric power being transmitted from the central unit accompanying at least the address and control signal, wherein at least the address and control signals transmitted from the central unit are respectively formed by arranging pulses alternately different in polarity, and substantially two trains of the address and control signals equal in contents but different only in the polarity are transmitted.

5. A system according to claim 4 wherein a predetermined voltage signal of one polarity is transmitted from the central unit also during the transmission of the response signal and thereafter another voltage signal of the same magnitude as but of the opposite polarity to said predetermined voltage signal is transmitted so that a circuit of the respective terminal units is short-circuited and opened and thereby the response signal is transmitted from the terminal units.

6. A system according to claim 5 wherein the electric power included in the signals transmitted from the central unit is accumulated in the power accumulating means in the respective terminal units by means of a full-wave rectification, and the address, control and the like signals included in said transmitted signals are provided to following circuits without being subjected to the full-wave rectification.

7. In a time division multiplex transmission apparatus comprising a central unit and a plurality of terminal units respectively connected to said central unit through a pair of bus lines, address and control signals respectively corresponding to said terminal units being transmitted sequentially in series from the central unit to the respective terminal units, and response signals being transmitted from the respective terminal units during periods between the preceding control signals and the following address signals;

an arrangement in which said central unit comprises

(a) a clock pulse generating circuit,

(b) a synchronizing signal circuit which receives output pulses from said clock pulse generating circuit,

(c) a start pulse generator which receives a first output signal from said synchronizing signal circuit to generate a start pulse,

(d) an address selecting circuit which receives a second output signal from the synchronizing signal circuit to select addresses,

(e) an address signal generating circuit which generates address signals from an output signal of said address selecting circuit responsive to a third output signal of the synchronizing signal circuit,

(f) a decoder for decoding the output signal of the address selecting circuit,

(g) an instruction setting circuit for setting instructions for the terminal units,

(h) an instruction reading circuit for reading contents of said instruction setting circuit which are corresponding to the addresses decoded by said decoder,

(i) a control signal generating circuit for generating control signals depending on the contents read by said instruction reading circuit in response to a fourth output signal of the synchronizing signal circuit,

(j) a signal summing circuit for arranging said start pulses, address signals and control signals in a predetermined order responsive to a fifth output signal of the synchronizing signal circuit,

(k) a combining circuit for providing output signals of said signal summing circuit to the bus lines and receiving through the bus lines said response signals from the terminal units,

(l) indicating circuits corresponding to the terminal units, and

(m) a driving circuit for driving said indicating circuits depending on the contents of the response signals received by said combining circuit;

and said terminal units respectively comprise

(a'"'"') a combining circuit for receiving the start pulses, address signals and control signals transmitted from said central unit through the bus lines,

(b'"'"') an address register for storing the address signals,

(c'"'"') a control register for storing the control signals,

(d'"'"') a discriminating circuit for comparing the contents of the address signals stored in said address register with a preliminarily set address in this discriminating circuit to detect any coincidence between them,

(e'"'"') an address coincidence memory for storing any coincidence detected by the discriminating circuit,

(f'"'"') a driving circuit connected to said control register and address coincidence memory to be actuated responsive to an output signal of the address coincidence memory and in accordance with the control signals stored in the control register,

(g'"'"') an operating circuit operated by said driving circuit, and

(h'"'"') a detecting circuit for detecting operating states of said operating circuit and transmitting a response signal depending on a detecting state of the operating circuit to the bus lines through the combining circuit in the terminal unit.