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CMOS polarity reversal circuit

  • US 4,139,880 A
  • Filed: 10/03/1977
  • Issued: 02/13/1979
  • Est. Priority Date: 10/03/1977
  • Status: Expired due to Term
First Claim
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1. A CMOS polarity reversal circuit having first and second input terminals and first and second output terminals, comprising:

  • a first P-channel MOS device having a source, drain and gate, the source being coupled to the first input terminal, the drain being coupled to the first output terminal, the gate being coupled to the second input terminal;

    a first N-channel MOS device having a source, drain and gate, the source being coupled to the first input terminal, the drain being coupled to the second output terminal, the gate being coupled to the second input terminal;

    a second P-channel MOS device having a source, drain and gate, the source being coupled to the second input terminal, the drain being coupled to the first output terminal, the gate being coupled to the first input terminal; and

    a second N-channel MOS device having a source, drain and gate, the source being coupled to the second input terminal, the drain being coupled to the second output terminal, and the gate being coupled to the first input terminal, thereby forming a circuit which will always provide a desired voltage polarity at the output terminals regardless of polarity of voltage applied to the input terminals.

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