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Logic state analyzer

  • US 4,139,903 A
  • Filed: 05/31/1977
  • Issued: 02/13/1979
  • Est. Priority Date: 03/31/1976
  • Status: Expired due to Term
First Claim
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1. An apparatus for use in the analysis of a digital device, by displaying visual representations of monitored device signals in response to the occurrence of preselected conditions, said apparatus comprising:

  • threshold circuitry for providing a threshold signal;

    input means coupled to said threshold circuitry for monitoring a plurality of device signals within said digital device and for providing a plurality of buffered device signals in response to said device signals and said threshold signal;

    timing generator means coupled to the input means for providing at least one timing signal in response to at least one of said buffered device signals;

    first storage means coupled to said input means and said timing generator means for storing electrical representations of said buffered device signals in response to at least one of said timing signals;

    trigger word means having a plurality of switchable elements for producing a plurality of trigger word signals in response to the setting of said switchable elements;

    pattern recognition means coupled to the first storage means, the trigger word means and the timing generator means for producing a first plurality of control signals in response to the electrical representations of said buffered device signals, said plurality of trigger word signals and one or more of said timing signals;

    trigger generator means having settable delay means and coupled to the pattern recognition means for providing a trigger signal in response to the setting of the settable delay means and said first plurality of control signals;

    memory control means coupled to the timing means and said trigger generator means for providing a memory input control signal in response to said timing signals and said trigger signal;

    first memory means coupled to the first storage means and to the trigger generator means for storing electrical representations of said buffered device signals in response to said memory input control signal and for providing a memory output signal in response to said stored electrical representations of said buffered device signals and an output control signal; and

    display means coupled to said first memory means and having control means for providing said output control signal and having means for providing an X position signal and a Y position signal in response to first and second predetermined portions, respectively, of said memory output signal, said display means causing visual indications to be displayed in positions within an X-Y coordinate display format in response to said X position signal and said Y position signal.

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