Auxiliary ROM memory system
First Claim
1. A system for providing hierarchied auxiliary read-only memory in addition to read-only memory on-board a central processing unit module comprising:
- (a) memory means for providing a plurality of memory categories including permanent read-only memory and alterable programmable read-only memory for data storage in excess or in lieu of on-board read-only memory and for implementation and installation of changes to on-board read-only memory respectively; and
(b) decoder means for recognition of addresses for accessing a given memory category of said memory means according to a predetermined hierarchy when the given accessing address falls within more than one or more overlapping subordinated address ranges for the memory categories of said memory means.
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Abstract
An auxiliary ROM memory system which is hierarchied for providing for the contingency of additional read-only memory control program storage requirements in excess or in lieu of the predetermined ROM memory provided on-board a microprocessor based central processing unit module, and a read-only memory altering capability utilizing programmable read-only memory to expedite the implementation/installation of changes to the ROM bit patterns. The alterable PROM storage comprises bulk PROM memory including a first PROM set that is mutually exclusive as to existing on-board ROM memory for addressably branching to code extensions and/or in-line code insertions, and/or a second PROM set that is mutually inclusive as to existent on-board and contingent ROM memory for decodably addressing large-scale code overlays thereto. In addition, the alterable PROM storage comprises patch PROM for addressing, through multi-leveled decoding, small-scale code overlays to the on-board and contingent ROM memory for single in-line bit pattern alterations. Conflicting memory requests involving addresses recognized by more than one of the supra memory categories, when enabled, are presented to a predetermined hierarchy of memory precedences for resolution thereof. Each of the enumerated memory categories of the auxiliary ROM memory system may be operative to have its population incremented or decremented without invalidating the above hierarchy of addressing.
65 Citations
68 Claims
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1. A system for providing hierarchied auxiliary read-only memory in addition to read-only memory on-board a central processing unit module comprising:
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(a) memory means for providing a plurality of memory categories including permanent read-only memory and alterable programmable read-only memory for data storage in excess or in lieu of on-board read-only memory and for implementation and installation of changes to on-board read-only memory respectively; and (b) decoder means for recognition of addresses for accessing a given memory category of said memory means according to a predetermined hierarchy when the given accessing address falls within more than one or more overlapping subordinated address ranges for the memory categories of said memory means.
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2. A hierarchied auxiliary memory system having structured ROM for use through a system bus as an adjunct to ROM on-board a central processing unit module for storage of instruction code comprising:
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(a) Contingent ROM memory means operatively coupled through the system bus to the central processing unit module for permanent storage of code in excess of or in lieu of that residing in the on-board ROM and said contingent ROM memory means; (b) Alterable PROM memory means operatively coupled through the system bus to the central processing unit module for storage of code implementation and installation of code changes to on-board ROM; and (c) Address Decoder means operatively coupled through the system bus to the central processing unit module for receipt of addresses therefrom for controlling the accessing of instruction code in said Contingency ROM memory means and said Alterable PROM memory means, and for ordered resolution according to a predetermined hierarchy for accessing precedence when memory ranges thereof overlap and therefore conflict by subordinating the former to the latter. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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40. A contingency ROM storage module operatively coupled through a system bus to a CPUM having on-board ROM for permanent data storage of instruction code in excess of or in lieu of code in the on-board ROM comprising:
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(a) Address Buffer means operative to receive addresses on the system bus from the CPUM for signal driving and correcting biasing therefor for correlative matching of signal levels; (b) Permanent ROM storage means having addressing ranges that are transferably equivalent to ROM on board the CPUM and operative to receive driven address signals from said Address Buffer means for accessing instruction data sets mask stored therein in a plurality of partitions for transmittal on the system bus; and (c) Instruction multiplexer means operative to receive instruction data from more than one partition of said permanent ROM storage means for selection of a instruction data set from one of the presented partitions according to a predetermined code of addresses received on the system bus from the CPUM for transmittal through the system bus to the CPUM. - View Dependent Claims (41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53)
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54. An alterable PROM storage module operatively coupled through a system bus to a central processing unit module having on-board ROM for programmable data storage of insturction code for implementation and installation of changes to the on-board ROM code comprising:
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(a) Bulk PROM means operative to receive accessing addressing through the system bus from the central processing unit module for accessing instruction code programmably stored therein according to mutuality of address assigning for extensions, insertions, and large-scale overlay to code in on-board ROM; (b) Patch PROM means operative to receive accessing addresses through the system bus from the central processing unit module for accessing instruction code programmably stored therein for single in-line bit pattern alterations through small-scale code overlay to code in on-board ROM; and (c) address decoding means operatively coupled to receive address signals through the system bus from the central processing unit module for accessing instruction code from said bulk PROM means according to a mutuality of assigned addresses for changing on-board ROM, and for accessing instruction code from said patch PROM means as single in-line bit pattern alterations to the on-board ROM, said address decoding means further includes; (1) first-level decoding means for partitioning said patch PROM means into a predetermined finite number of locations, and operative to receive a first portion of the address on the system bus for selecting a unique location from the set of locations through the generation of a psuedo address therefor; and (2) second-level decoding means operative to receive the psuedo address from said first-level decoding means for pointing to a particular group as a subset of the selected location, and operative to receive a second portion of the address on the system bus for identifying a byte pointer to a multi-byte segment of the particular group. - View Dependent Claims (55, 56, 57, 58)
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59. A memory system for providing programmable extensions, insertion, and large-scale overlay to bulk code through a system bus to ROM on board a central processing unit module comprising:
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(a) programmable read-only memory means operatively coupled to the system bus for storage of instruction code for transmittal upon command to the central processing unit module; and (b) address decoding means operatively coupled to receive address signals through the system bus from the central processing unit module for accessing instruction code from said programmable read-only memory means according to a mutuality of assigned addresses for changing on-board ROM, wherein said address decoding means further includes means for specifying said programmable read-only memory means into a predetermined address range area and designating a subset of these address range areas as address effective areas, and for allowing one or more of the address effective areas to contain all or part of the instruction code. - View Dependent Claims (65, 66)
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60. A memory system for providing programmable extensions, insertion, and large-scale overlay of bulk code through a system bus to ROM on board a central processing unit module comprising:
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(a) programmable read-only memory means operatively coupled to the system bus for storage of instruction code for transmittal upon command to the central processing unit module; and (b) address decoding means operatively coupled to receive address signals through the system bus from the central processing unit module for accessing instruction code from said programmable read-only memory means according to a mutuality of assigned addresses for changing on-board ROM, wherein said address decoding means further includes means for instituting the mutuality of assigned addresses in a mutually exclusive mode for extensions and insertions of code to on-board ROM. - View Dependent Claims (63)
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61. A memory system for providing programmable extensions, insertion, and large-scale overlay of bulk code through a system bus to ROM on board a central processing unit module comprising:
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(a) programmable read-only memory means operatively coupled to the system bus for storage of instruction code for transmittal upon command to the central processing unit module; and (b) address decoding means operatively coupled to receive address signals through the system bus from the central processing unit module for accessing instruction code from said programmable read-only memory means according to a mutuality of assigned addresses for changing on-board ROM, wherein said address decoding means further includes means for instituting the mutuality of assigned addresses in a mutually inclusive mode for large-scale code overlay on-board ROM. - View Dependent Claims (64)
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62. A memory system for providing programmable extensions, insertion, and large-scale overlay of bulk code through a system bus to ROM on board a central processing unit module comprising:
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(a) programmable read-only memory means operatively coupled to the system bus for storage of instruction code for transmittal upon command to the central processing unit module; (b) address decoding means operatively coupled to receive address signals through the system bus from the central processing unit module for accessing instruction code from said programmable read-only memory means according to a mutuality of assigned addresses for changing on-board ROM; and (c) patch memory means operatively coupled to the system bus for single in-line bit pattern alterations to read-only memory on-board the central processing unit module for allowing said programmable read-only memory means to be accessed through said address decoding means by addresses patched into the on-board ROM by said patch memory means.
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67. A memory system for providing programmable small-scale overlay patches to a system bus read-only memory on board a central processing unit module for single-in-line-bit pattern alterations through a system bus to a central processing unit module comprising:
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(a) programmable read-only memory means operatively coupled to the system bus for storage of instruction code for transmittal upon command to the central processing module; and (b) address decoding means operatively coupled to receive address signals through the system bus from the central processing unit module for accessing instruction code from said programmable read-only memory means as single-in-line-bit pattern alterations to the on-board ROM, wherein said address decoding means further includes; (1) first-level decoding means for partitioning the programmable read-only memory into a predetermined finite number of locations, and operative to receive a first portion of the address on the system bus for selecting a unique location from the set of locations through the generation of a psuedo address therefor; and (2) second-level decoding means operative to receive the psuedo address from said first-level decoding means for pointing to a particular group as a subset of the selected location, and operative to receive a second portion of the address on the system bus for identifying a byte pointer to a multi-byte segment of the particular group. - View Dependent Claims (68)
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Specification