Semiconductor process using lapped substrate and lapped low resistivity semiconductor carrier

• US 4,141,135 A
• Filed: 10/12/1976
• Issued: 02/27/1979
• Est. Priority Date: 10/14/1975
• Status: Expired due to Term

• Current Assignee: Thomson-CSF (Thales SA)
• Original Assignee: Thomson-CSF (Thales SA)
• Inventors: Henry, Raymond, Bouvet, Jean-Victor
• Primary Examiner(s): Larkins, William D.
• Application Number:
  US05/731,213
• Time in Patent Office: 868 Days
• Field of Search: 29/580, 29/583, 29/589, 29/591, 357/56, 357/81
• US Class Current: 438/108
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 23/045 the other leads having an insulating passage through the base
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10157 at the active surface

Abstract

A process intended for avoiding the "flip chip bonding" technique, well known for planar diodes, is provided. It is further applicable to mesa diodes and planar transistors. It comprises an essential step: the lapping of the substrate up to reduce its thickness to the same order of magnitude as the upper active layer of a semiconductor device, thus facilitating the cooling of the device through the substrate towards a heat sink. This essential step is made possible by virtue of a preliminary bonding on the upper layer of the semiconductor device of a block of silicon. According to a first alternative of the invention the block is finally eliminated and the device is a conventional one with a very thin substrate. According to a second alternative of the invention, the block is retained and lapped after addition of the heat sink, then metalized to provide a secondary way to the thermal flux.

Claims

1. A process for producing semiconductor devices of planar diode type, with a very low thermal resistance, starting from a wafer consisting of a substrate, at least one active layer of semiconductor material exhibiting electrodes and a metal coating, said process comprising the following steps:

(a) bonding of a block of low resistivity semiconductor material onto said active part;

(b) lapping of said substrate;

(c) finishing the device according to the following sub-steps;

(c₁) depositing a first layer of highly heat conductive metal onto the lapped substrate;

(c₂) depositing a second layer of low resistivity metal onto said first layer;

(c₃) lapping of the block;

(c₄) metallising the lapped block surface by a highly heat conductive metal.

2. A process for producing semiconductor devices of mesa diode type with a very low thermal resistance, starting from a wafer consisting of a substrate supporting mesa diode structures protected by a passivation layer except at the tops of the mesa structures whereon a metallic coating is deposited, said process comprising the following steps:

(a) depositing a thick layer of glass between said mesa structures filling the gaps between said structures and laying bare said metal coatings;

(b) bonding of a block of low resistivity semiconductor material onto said metal coatings;

(c) lapping of said substrate;

(d) finishing the device according to the following sub-steps;

(d₁) depositing a first layer of highly heat conductive metal onto the lapped substrate;

(d₂) depositing a second layer of low resistivity metal onto said first layer;

(d₃) lapping of the block;

(d₄) metallising the lapped block surface by a highly heat conductive metal.

3. A process for producing semiconductor devices of transistor type, with a very low thermal resistance, starting from a transistor device comprising a substrate, interleaved emitter and base regions and finger shaped metallisations in contact with said regions and leading respectively to a common emitter stump and to a common base stump, said process comprising the following steps:

(a) depositing a layer of insulating material onto said finger shaped metallisations;

(b) forming windows in said layer, laying bare said emitter fingers;

(b) bonding a block of low resistivity semiconductor material onto said metallisation, partially covering said finger shaped metallisations;

(d) lapping of said substrate;

(e) finishing of the device according to the following sub-steps;

(e₁) depositing a first layer of highly conductive metal onto the lapped substrate;

(e₂) depositing a second layer of low resistivity metal onto the first layer;

(e₃) lapping of the block;

(e₄) metallising of the lapped block surface by a highly heat conductive metal.