Multi-frequency digital wave synthesizer for providing analog output signals
First Claim
1. A multi-frequency digital wave synthesizer, including a system clock, for providing one of a plurality of analog output signals made up of n successive segments wherein n is an integer greater than one, in response to a corresponding electrical digital signal input, comprising:
- (a) logic array means for storing and providing a binary representation of the period of a selected segment of any of the plurality of output signals;
(b) addressing means operatively connected to receive a binary identification of a selected segment, to the logic array means and to the digital signal input for addressing a selected segment, whereby the logic array means provides a binary representation of the period of the selected segment;
(c) segment period determining means, operatively connected to the output of the logic array means and responsive to the binary representation for providing in real time the period of the selected segment;
(d) segment selecting means connected to receive and responsive to the output of the segment period determining means, for successively providing a binary identification of each of the n segments, having output means operatively connected to the addressing means; and
(e) wave generator means, operatively connected to the output means of the segment selecting means for identifying the segment and to the output of the segment period determining means for providing the real time period, for selectively providing a predetermined voltage corresponding to the selected segment period, successively, for each of the n segments thereby forming one of the plurality of analog output signals.
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Abstract
A digital wave synthesizer provides one of a plurality of available analog output signals in response to and corresponding to a digital input signal. Each of the available plurality of analog output signals is made up of n successive segments of periods A and B. Segment information is stored in a logic array in such a manner that the segment number and the desired frequency output provides any of the n segments of any of the plurality of analog output signals with the appropriate A or B period. The successive order of segments is not altered by a change in the digital input signal requiring a change in the output signal frequency. An increase in frequency simply requires that a succeeding segment have a shorter A or B period and that a lower frequency have a longer A or B period. The voltage provided in a voltage distribution network is always the same for a particular number of segments irrespective of the output frequency required. Therefore, when a frequency change is required, there is no voltage shift.
19 Citations
46 Claims
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1. A multi-frequency digital wave synthesizer, including a system clock, for providing one of a plurality of analog output signals made up of n successive segments wherein n is an integer greater than one, in response to a corresponding electrical digital signal input, comprising:
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(a) logic array means for storing and providing a binary representation of the period of a selected segment of any of the plurality of output signals; (b) addressing means operatively connected to receive a binary identification of a selected segment, to the logic array means and to the digital signal input for addressing a selected segment, whereby the logic array means provides a binary representation of the period of the selected segment; (c) segment period determining means, operatively connected to the output of the logic array means and responsive to the binary representation for providing in real time the period of the selected segment; (d) segment selecting means connected to receive and responsive to the output of the segment period determining means, for successively providing a binary identification of each of the n segments, having output means operatively connected to the addressing means; and (e) wave generator means, operatively connected to the output means of the segment selecting means for identifying the segment and to the output of the segment period determining means for providing the real time period, for selectively providing a predetermined voltage corresponding to the selected segment period, successively, for each of the n segments thereby forming one of the plurality of analog output signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. An electronic multi-frequency digital wave synthesizer, implemented as integrated circuitry in semiconductor substrate material, including a system clock, for providing one of a plurality of analog output signals made up of n successive segments wherein n is an interger greater than one, in response to a corresponding electrical digital signal input, comprising:
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(a) logic array means for storing and providing a binary representation of the period of a selected segment of any of the plurality of output signals, wherein the n segments of each of the plurality of output signals equals x segments + y segments wherein x and y are integers and wherein the n segments of each of the plurality of output signals are divided into A periods and B periods wherein A and B are different integers; (b) addressing means operatively connected to receive a binary identification of a selected segment, to the logic array means for addressing a selected segment, whereby the logic array means provides a binary representation of the period of the selected segment; (c) segment period determining means operatively connected to the output of the logic array means and responsive to the binary representation for providing in real time the A period or the B period of the selected segment; (d) segment counting means responsive to the segment period determining means, for sequentially counting the occurrence of each segment and providing at its output a binary count thereof to the addressing means; and (e) voltage wave generator means, operatively connected to the output of the segment counting means for identifying the segment and to the output of the segment period determining means for providing successively n/2 predetermined voltages each corresponding to a selected segment for the duration (A and B) of the segment period for each of the n segments. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. In a multi-frequency digital wave synthesizer for providing one of a plurality of analog output signals made up of n successive segments wherein n is an integer greater than one, in response to a corresponding electrical digital signal input, the method of providing an analog output signal comprising the steps of:
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(a) storing in logic array means the binary representation of the periods of the n successive segments for all of the plurality of analog output signals; (b) addressing the logic array means including inputting the digital signal input to provide the binary representation of the addressed segment; (c) changing the binary representation provided from the logic array means to the segment period in real time by counting a counter using a fixed frequency; (d) selecting a voltage level and providing that level as an output during the segment period to form one of the plurality of analog output signals; (e) counting the segments and providing the next count to the logic array means to address the next sequential segment; and (f) repeating steps b through e until the waveform has been completed. - View Dependent Claims (35)
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36. A multi-frequency digital sine wave synthesizer, including a system clock, for providing one of a plurality of analog output signals made up of n successive segments wherein n is an integer greater than one, in response to a corresponding electrical digital signal input, comprising:
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(a) logic array means for storing and providing a binary representation of the period of a selected segment of any of the plurality of output signals; (b) addressing means operatively connected to receive a binary identification of a selected segment, to the logic array means and to the digital signal input for addressing a selected segment, whereby the logic array means provides a binary representation of the period of the selected segment; (c) segment period determining means, operatively connected to the output of the logic array means and responsive to the binary representation for providing in real time the period of the selected segment; (d) segment selecting means connected to receive and responsive to the output of the segment period determining means, for successively providing a binary identification of each of the n segments, having output means operatively connected to the addressing means; and (e) wave generator means, operatively connected to the output means of the segment selecting means for identifying the segment and to the output of the segment period determining means for providing the real time period, for selectively providing a predetermined voltage corresponding to the selected segment period, successively, for each of the n segments thereby forming one of the plurality of analog output signals, a wave generator means comprising; (i) a capacitor ladder network comprising a plurality of capacitors having their first terminals connected together to a common point; (ii) a source of reference voltage; and (iii) a register, selectively loadable from the segment selecting means, each stage of the counter being connected to the second terminal of a respective one of a plurality of capacitors and to the reference voltage, the capacitor values being selected to provide an output voltage when the associated stage is loaded, such that the desired analog output signal is sequentially produced as the stages of the register are loaded. - View Dependent Claims (37, 38, 39, 40, 41, 42)
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43. An electronic multi-frequency digital sine wave synthesizer, implemented as integrated circuitry in semiconductor substrate material, including a system clock, for providing one of a plurality of analog output signals made up of n successive segments wherein n is an integer greater than one in response to a corresponding electrical digital input, comprising:
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(a) logic array means for storing and providing a binary representation of the period of a selected segment of any of the plurality of output signals, wherein the n segments of each of the plurality of output signals x segments + y segments wherein x and y are integers and wherein the n segments of each of the plurality of output signals are divided into A periods and B periods wherein A and B are different integers; (b) addressing means operatively connected to receive a binary identification of a selected segment and to the logic array means for addressing a selected segment, whereby the logic array means provides a binary representation of the period of the selected segment; (c) segment period determining means operatively connected to the output of the logic array means in response to the binary representation for providing in real time the A period or the B period of the selected segment; (d) segment counting means responsive to the segment period determining means, for sequentially counting the occurrence of each segment and providing at its output a binary count thereof to the addressing means; and (e) voltage wave generator means, operatively connected to the output means of the segment selecting means for identifying the segment and to the output of the segment period determining means for providing the real time period, for selectively providing a predetermined voltage corresponding to the selected segment period, successively, for each of the n segments thereby forming one of the plurality of analog output signals, a wave generator means comprising; (i) a capacitor ladder network comprising a plurality of capacitors having their first terminals connected together to a common point; (ii) a source of reference voltage; and (iii) a register, selectively loadable from the segment selecting means, each stage of the counter being connected to the second terminal of a respective one of a plurality of capacitors and to the reference voltage, the capacitor values being selected to provide an output voltage when the associated stage is loaded, such that the desired analog output signal is sequentially produced as the stages of the register are loaded. - View Dependent Claims (44, 45, 46)
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Specification