Method and apparatus for generating tone signals and the like

• US 4,143,327 A
• Filed: 07/08/1977
• Issued: 03/06/1979
• Est. Priority Date: 07/08/1977
• Status: Expired due to Term

• Current Assignee: Kimball International Incorporated (HNI Corporation)
• Original Assignee: Kimball International Incorporated (HNI Corporation)
• Inventors: Welsh, Alan B.
• Primary Examiner(s): Heyman, John S.
• Application Number:
  US05/813,824
• Time in Patent Office: 606 Days
• Field of Search: 328/48, 328/129, 328/60, 328/61, 84/1.11, 84/1.19
• US Class Current: 327/114
• CPC Class Codes: G06F 7/68 using pulse rate multipliers or dividers pulse rate multipliers or dividers per seG06F7/70 takes precedence ; frequency division in electronic watches G04G3/02; frequency multiplication or division in oscillators H03B19/00; frequency dividing counters per se H03K23/00 - H03K29/00
• CPC Class Codes: G10H 5/06 tones generated by frequency multiplication or division of a basic tone

Abstract

A method and apparatus for generating tone signals and the like in which a given frequency is employed for controlling a counter arrangement at a frequency which is equal to the frequency of the given signal multiplied by a factor other than a whole number. The multiplied frequency output when divided down will yield a frequency differing a desired amount from the given frequency.

Claims

1. A pulse generating circuit comprising:

first binary counter means having a clock terminal and a clear terminal and a plurality of least significant bits output terminals and a plurality of most significant bits output terminals, second binary counter means having clock terminal means and load terminal means and output terminal means which pulses at a predetermined count in said second counter means and also having input terminal means for loading a count in said second counter means, latch means interposed between the input terminal means of said second counter means and the most significant bits output terminals of said first counter means, means for clocking said first and second counter means at a first higher frequency, first means for clocking said latch means at a second lower frequency, and second means for clearing said first counter means after clocking of said latch means, the frequency of the pulses at the output terminal means of said second counter means differing a small amount from a whole multiple of said second frequency.

2. A pulse generating circuit according to claim 1 which includes means for squaring the pulses from the output terminal means of said second counter means.

3. A pulse generating circuit according to claim 1 which includes means for squaring the pulse from the output terminal means of said second counter means and for dividing the frequency thereof to provide a pulse train having a frequency near but not equal to the said second frequency.

4. A pulse generating circuit according to claim 1 in which said second counter means comprises a pair of modulo counters each having an output terminal which pulses at a respective count in the pertaining counter, the pulse frequencies at the output terminals of said second counters differing a small amount from one another.

5. A pulse generating circuit according to claim 4 which includes means for squaring the pulses from the output(s) terminals of said modulo counters.

6. A pulse generating circuit according to claim 4 which includes means for squaring the pulses from the output terminals of said second modulo counters and for dividing the frequency thereof to provide pulse trains having frequencies near but different from said second frequency by respective amounts.

7. A pulse generating circuit according to claim 3 which includes a combining network in which said pulse train and said means for clocking said latch means are combined to form a single output.

8. A pulse generating circuit according to claim 6 which includes a combining network in which said pulse trains and said means for clocking said latch means are combined to form a single output.

9. A pulse generating circuit according to claim 1 in which said latch means inverts the signal at the output terminals of said first counter means.

10. The pulse generating circuit according to claim 1 wherein said second counter means is of the modulo type.

11. A pulse generating circuit according to claim 10 wherein the input terminal means of said second counter means are fewer in number than the combined output terminals of said first counter means, and said latch means is interposed between the input terminal means of said second counter means and the output terminals of said first counter means starting with the most significant bits terminals.

12. A pulse generating circuit according to claim 1 wherein said second means for clearing said first counter means clears said first counter means immediately after the clocking of said latch means.

13. A method of generating a pulse train having a frequency which differs a predetermined amount from a whole multiple of a reference frequency which comprises:

supplying clock pulses at a higher frequency and supplying further reference pulses at a frequency lower than said higher frequency, repetitively counting the number of clock pulses during a cycle of said reference frequency and representing the count in the form of a first binary word, transferring a predetermined number less than the total number of the bits of said first binary word commencing at the most significant end of the word to a place of storage to form a second binary word of smaller value than said first binary word, transferring said predetermined number of bits at the beginning of each cycle of the reference frequency, repetitively counting off at least one of;

the second binary word and the binary compliment thereof, during the respective cycle of said reference frequency and generating a pulse at the end of each said counting off to form a pulse train having a frequency differing a small amount from a whole multiple of said reference frequency.

14. The method according to claim 13 in which said transferred bits are inverted in said place of storage.

15. The method according to claim 14 which includes additionally counting off a binary word differing a small amount from said one of said second binary word and the complement thereof to generate additional pulses, and squaring said additional pulses to form a further pulse train differing in frequency a small amount from the other generated pulse train.

16. The method according to claim 13 which includes dividing the pulse train frequency down to produce pulses at a frequency differing a small amount from said reference frequency.

17. The method according to claim 13 which includes dividing both said pulse train frequencies down to produce pulses at frequencies which differ a small amount from each other and from said reference frequency.

18. The method according to claim 13 including squaring the pulses generated at the end of each said counting off.