Cascadable analog to digital converter

• US 4,144,525 A
• Filed: 10/21/1977
• Issued: 03/13/1979
• Est. Priority Date: 10/21/1977
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Inventors: O'Neill, John F.
• Primary Examiner(s): Miller, Charles D.
• Application Number:
  US05/844,229
• Time in Patent Office: 508 Days
• Field of Search: 340/347 M, 340/347 AD, 324/99 D
• US Class Current: 341/156
• CPC Class Codes: H03M 1/16 with scale factor modification, i.e. by changing the amplification between the steps H03M1/141 takes precedence
• CPC Class Codes: H03M 1/44 Sequential comparisons in series-connected stages with change in value of analogue signal
• CPC Class Codes: H03M 1/56 Input signal compared with linear ramp

Abstract

A circuit for converting an input analog signal into a digital representation and a remainder signal is disclosed. The digital representation is generated by a coder that counts an integral number of clock cycles during an interval in which the magnitude of the input analog signal is compared with the magnitude of a ramp signal. The remainder signal is generated by duration-to-amplitude conversion of a pulse whose duration is the fractional remainder of the final uncounted clock cycle.

Claims

1. A circuit for converting an analog signal level into a digital approximation and a remainder signal, said remainder signal being a measure of the error between the analog signal level and the digital approximation, including means for converting the analog signal level into a duration modulated signal and means for counting discrete events of a timing signal during the duration of said duration modulated signal,

characterized by:

means responsive to an interval between the termination of the duration modulated signal and a timing signal discrete event which is adjacent in time to said termination, for generating the remainder signal.

2. A ciruit according to claim 1 wherein the converting means includes means for comparing the magnitude of the analog signal level with the magnitude of a time varying signal.

3. A circuit according to claim 1 wherein the generating means includes duration-to-amplitude conversion.

4. A circuit according to claim 3 wherein amplification is controllably provided in the duration-to-amplitude conversion process.

5. A circuit according to claim 1 wherein the generating means is responsive to the interval extending between the termination of the duration modulated signal and the next discrete event of the timing signal for generating a complementary remainder signal.

6. In a multistage analog to digital converter wherein each stage generates a portion of a digital representation of an analog signal level, the portion being formed by means for counting discrete events of a timing signal occurring during a first time interval representing the analog signal level,

characterized by:

means responsive to the termination of the first time interval and a time adjacent discrete event of the timing signal for generating a second time interval, said second time interval being a measure of the error between the analog signal level and the digital representation of the analog signal level; and

means for effectively amplifying said second time interval by a predetermined factor.

7. In a converter according to claim 6 wherein the predetermined factor is proportional to the highest possible number count of said one portion;

whereby the amplification is inversely proportional to the resolution.

8. In a converter according to claim 6 wherein the amplifying means includes means for performing duration-to-amplitude conversion and amplitude-to-duration conversion.

9. In a converter according to claim 6 wherein the second time interval extends between the termination of the first time interval and the next discrete event of the timing signal to thereby form a complementary remainder signal.