System and method for increasing microprocessor output data rate

• US 4,144,562 A
• Filed: 06/23/1977
• Issued: 03/13/1979
• Est. Priority Date: 06/23/1977
• Status: Expired due to Term

• Current Assignee: NCR Corporation
• Original Assignee: NCR Corporation
• Inventors: Cooper, Paul J.
• Primary Examiner(s): Thomas, James D.
• Application Number:
  US05/809,496
• Time in Patent Office: 628 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/307
• CPC Class Codes: G06F 13/4217 with synchronous protocol
• CPC Class Codes: G06F 15/7864 on more than one IC chip

Abstract

A system and method is disclosed wherein a microprocessor having an eight-bit data bus and a sixteen-bit address bus is interconnected with a peripheral device to which a certain amount of data must be transferred at a data rate greater than is possible by utilizing the eight-bit data bus to accomplish the transfer. The system includes a microprocessor, a memory, and a peripheral device interconnected by the eight-bit data bus, the sixteen-bit address bus and a read-write conductor. The peripheral device includes an address code recognition circuit coupled to the data bus and one of the address lines, and also includes a fifteen-bit buffer connected to fifteen lines of the address bus. The address code recognition circuit generates an output which is gated with the read-write conductor to generate a clock signal which enables the data on the address bus to be loaded into the fifteen-bit buffer, from which it may be utilized by the peripheral device. During two microprocessor read cycles, two eight-bit bytes of data are loaded from the memory into the microprocessor via the data bus. Fifteen of these sixteen bits constitute data to be rapidly transferred to the peripheral device, and one bit is programmed as an enable bit to be inputted to the address code recognition circuit. During another microprocessor read cycle, another eight-bit byte including a peripheral address code is loaded from the memory into the microprocessor via the data bus. During a first portion of a microprocessor write cycle, the fifteen bits of data to be transferred to the peripheral device and the enable bit are outputted on the address bus. During a second portion of the same write cycle, the peripheral address code is out-putted on the data bus. If the enable bit is programmed to be a "1", and the peripheral address code is the one that the address code recognition circuit is set up to recognize, the code recognition circuit generates an enable signal which in turn is ANDed with a write pulse from the read-write conductor to produce a clock enable signal which enables the fifteen bits of data to be loaded into the fifteen-bit buffer. The fifteen bits of data are then available for utilization by the peripheral device.

Claims

1. A data processing system comprising:

(a) a processor having a control output, said control output indicating in part a data word greater than the number of data lines;

(b) a memory;

(c) a utilization device;

(d) address lines and data lines operatively coupling said processor to said memory, said address lines being substantially greater in number than said data lines;

(e) selection means coupling said utilization device to a plurality of said data lines for selecting said utilization device in response to a code transferred to said selection means via said plurality of data lines and for producing an address code recognition signal in response to said code;

(f) buffer means coupling said utilization device to a plurality of said address lines for storing a data word transferred from said processor to said buffer means via said plurality of address lines in response to said address code recognition signal by said selection means and the control output from said processor; and

(g) means associated with said processor for enabling data flow from said processor to said address lines when the number of data lines is insufficient to carry a data word.

2. The data processing system according to claim 1 wherein said code is a peripheral address code.

3. The data processing system according to claim 1 wherein one of said address lines is coupled to said selection means and said selection means includes means responsive to said one of said address lines for enabling said selecting of said utilization device.

4. The data processing system as recited in claim 1 wherein at least one of said data lines is coupled to said buffer means to effect transferring a portion of said data word to said buffer means.

5. The data processing system according to claim 1 wherein said processor includes an accumulator coupled to said data lines for temporarily storing said code and includes program counter means coupled to said data lines and to said address lines for temporarily storing said data word.

6. A method of operating a data processing system, of the type having a larger number of address lines than data lines, so as to enable the transfer of a magnitude of data greater than that transferable on the data lines, comprising the steps of:

(a) temporarily storing a peripheral address code in a processor;

(b) temporarily storing a data word in said processor, said data word having a larger number of bits than said peripheral address code;

(c) transferring said data word to a peripheral device via an address bus during a machine cycle;

(d) transferring said peripheral address code to said peripheral device via a data bus during said machine cycle;

(e) enabling loading of said data word into a buffer of said peripheral device in response to recognition of said peripheral address code by a code recognition circuit of said peripheral device.

7. The method set forth in claim 6 wherein said method includes the steps of fetching said peripheral address code and said data word from a memory via said data bus.

8. The method set forth in claim 6 wherein said method includes the steps of initially computing said data word prior to the temporary storing thereof and also includes the step of computing said peripheral address code prior to the temporary storing thereof.

9. The method set forth in claim 6 including the step of temporarily storing an address bit, in addition to said address code, in said processor and transferring said address bit to said peripheral device during said machine cycle to enable recognition of said peripheral address code by said peripheral device.

10. The method as recited in claim 6 further including the step of transferring a portion of said data word to said peripheral device via a portion of said data bus.