High power MOS device and fabrication method therefor

• US 4,145,703 A
• Filed: 04/15/1977
• Issued: 03/20/1979
• Est. Priority Date: 04/15/1977
• Status: Expired due to Term

• Current Assignee: Supertex Incorporated (Microchip Technology Incorporated)
• Original Assignee: Supertex Incorporated (Microchip Technology Incorporated)
• Inventors: Blanchard, Richard A., Choy, Benedict C. K.
• Primary Examiner(s): Wojciechowicz, Edward J.
• Application Number:
  US05/787,788
• Time in Patent Office: 704 Days
• Field of Search: 357/23, 357/55, 357/54, 357/59
• US Class Current: 257/331
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

This disclosure relates to a high power VMOS semiconductor device and fabrication method therefor. This VMOS semiconductor device uses a doped polysilicon gate electrode in the V groove and an overlying metal electrode located over an insulation layer protecting the doped polysilicon gate electrode. This overlying metal electrode layer covers substantially the entire surface area (except for a small area where electrical contact is made to the doped polysilicon gate electrode) of one surface of the device. Another embodiment discloses the use of a self-aligned metal contact to the source or drain region of the VMOS device between adjacent V grooves.

Claims

1. A high power MOS semiconductor device comprising, in combination, a semiconductor substrate, spaced source and drain regions of one conductivity type located in said semiconductor substrate, substantially V-shaped channel region having a region thereof of opposite conductivity type connected to said source region and to said drain region and providing a groove in said semiconductor substrate, a first insulating layer located in said groove in said semiconductor substrate and on said substantially V-shaped channel region, a doped electrically conductive polysilicon gate electrode layer located in said groove and on said first insulating layer, a second insulating layer located on and covering said polysilicon gate electrode layer, a first electrode electrically connected to one of said source and drain regions, and a second electrode electrically connected to the other of said source and drain regions, one of said first and second electrodes being located on said second insulating layer and covering substantially the entire surface area over one surface of said semiconductor substrate.

2. A high power MOS semiconductor device in accordance with claim 1 wherein said one of said first and second electrodes located on said second insulating layer being electrically connected to one of said source and drain regions and to one of said regions of opposite conductivity type.

3. A high power MOS semiconductor device in accordance with claim 2 wherein said one of said first and second electrodes being the source electrode and the other of said first and second electrodes being the drain electrode.

4. A high power MOS semiconductor device in accordance with claim 3 wherein said spaced source and drain regions are of N type conductivity and said regions of said opposite conductivity type of said V-shaped channel region being of P type conductivity.

5. A high power MOS semiconductor device in accordance with claim 1 wherein said spaced source and drain regions of said one conductivity type being located on opposite sides of said V-shaped channel region, said regions of said V-shaped channel region of opposite conductivity type surrounding a substantial portion of said spaced source and drain regions of said one conductivity type, a high resistivity region of said one conductivity type having a higher resistivity than the resistivity of said spaced source and drain regions surrounding a substantial portion of said regions of opposite conductivity type, and a low resistivity region of said one conductivity type having a lower resistivity than the resistivity of said high resistivity region of said one conductivity type located in contact with said high resistivity region of said one conductivity type.

6. A high power MOS semiconductor device in accordance with claim 5 wherein said one of said first and second electrodes located on said second insulating layer being electrically connected to one of said source and drain regions and to one of said regions of opposite conductivity type, said one of said first and second electrodes being the source electrode and the other of said first and second electrodes being the drain electrode, said spaced source and drain regions are of N type conductivity and said regions of said opposite conductivity type of said V-shaped channel region being of P type conductivity, and a third electrode electrically connected to said polysilicon gate electrode through an opening in said second insulating layer located over said one surface of said semiconductor substrate.

7. A high power MOS semiconductor device comprising, in combination, a semiconductor substrate, spaced source and drain regions of one conductivity type located in said semiconductor substrate, a pair of spaced substantially V-shaped channel regions, each of said pair of spaced substantially V-shaped channel regions having a region thereof of opposite conductivity type connected to said source region and to said drain region and providing a groove in said semiconductor substrate, a first insulating layer located in each groove in said semiconductor substrate and on each of said pair of spaced substantially V-shaped channel regions, a second insulating layer located in each groove and on said first insulating layer, a doped electrically conductive polysilicon gate electrode layer located in each said groove and on said second insulating layer, a third insulating layer located on and covering said polysilicon gate electrode layer, a first electrode electrically connected to one of said source and drain regions, and a second electrode electrically connected to the other of said source and drain regions, one of said first and second electrodes being located on said third insulating layer and covering substantially the entire surface area over one surface of said semiconductor substrate.

8. A high power MOS semiconductor device in accordance with claim 7 wherein said one of said first and second electrodes located on said third insulating layer being electrically connected to one of said source and drain regions and to one of said regions of opposite conductivity type.

9. A high power MOS semiconductor device in accordance with claim 7 wherein said one of said first and second electrodes located on said third insulating layer being electrically connected to one of said source and drain regions on a substrate surface portion between said pair of spaced substantially V-shaped channel regions.

10. A high power MOS semiconductor device in accordance with claim 9 wherein said one of said first and second electrodes being the source electrode and the other of said first and second electrodes being the drain electrode.

11. A high power MOS semiconductor device in accordance with claim 10 wherein said spaced source and drain regions are of N type conductivity and said regions of said opposite conductivity type of said V-shaped regions being of P type conductivity.

12. A high power MOS semiconductor device in accordance with claim 7 wherein said first insulating layer being silicon dioxide and said second insulating layer being silicon nitride.

13. A high power MOS semiconductor device in accordance with claim 9 wherein said first insulating layer being silicon dioxide, said second insulating layer being silicon nitride, and said third insulating layer being silicon dioxide.

14. A VMOS semiconductor device comprising, in combination, a semiconductor substrate region, spaced source and drain regions of one conductivity type located in said semiconductor substrate region, substantially V-shaped channel region having a region thereof of opposite conductivity type connected to said source region and to said drain region and providing a groove in said semiconductor substrate region, at least one insulating layer located in said groove in said semiconductor substrate region and on said substantially V-shaped channel region, a doped electrically conductive polysilicon gate electrode layer located in said groove and on said insulating layer, another insulating layer located on and covering said polysilicon gate electrode layer, a first electrode electrically connected to one of said source and drain regions, and a second electrode electrically connected to the other of said source and drain regions, one of said first and second electrodes being located on said another insulating layer.