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High power MOS device and fabrication method therefor

  • US 4,145,703 A
  • Filed: 04/15/1977
  • Issued: 03/20/1979
  • Est. Priority Date: 04/15/1977
  • Status: Expired due to Term
First Claim
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1. A high power MOS semiconductor device comprising, in combination, a semiconductor substrate, spaced source and drain regions of one conductivity type located in said semiconductor substrate, substantially V-shaped channel region having a region thereof of opposite conductivity type connected to said source region and to said drain region and providing a groove in said semiconductor substrate, a first insulating layer located in said groove in said semiconductor substrate and on said substantially V-shaped channel region, a doped electrically conductive polysilicon gate electrode layer located in said groove and on said first insulating layer, a second insulating layer located on and covering said polysilicon gate electrode layer, a first electrode electrically connected to one of said source and drain regions, and a second electrode electrically connected to the other of said source and drain regions, one of said first and second electrodes being located on said second insulating layer and covering substantially the entire surface area over one surface of said semiconductor substrate.

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