High power MOS device and fabrication method therefor
First Claim
1. A high power MOS semiconductor device comprising, in combination, a semiconductor substrate, spaced source and drain regions of one conductivity type located in said semiconductor substrate, substantially V-shaped channel region having a region thereof of opposite conductivity type connected to said source region and to said drain region and providing a groove in said semiconductor substrate, a first insulating layer located in said groove in said semiconductor substrate and on said substantially V-shaped channel region, a doped electrically conductive polysilicon gate electrode layer located in said groove and on said first insulating layer, a second insulating layer located on and covering said polysilicon gate electrode layer, a first electrode electrically connected to one of said source and drain regions, and a second electrode electrically connected to the other of said source and drain regions, one of said first and second electrodes being located on said second insulating layer and covering substantially the entire surface area over one surface of said semiconductor substrate.
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Abstract
This disclosure relates to a high power VMOS semiconductor device and fabrication method therefor. This VMOS semiconductor device uses a doped polysilicon gate electrode in the V groove and an overlying metal electrode located over an insulation layer protecting the doped polysilicon gate electrode. This overlying metal electrode layer covers substantially the entire surface area (except for a small area where electrical contact is made to the doped polysilicon gate electrode) of one surface of the device. Another embodiment discloses the use of a self-aligned metal contact to the source or drain region of the VMOS device between adjacent V grooves.
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Citations
14 Claims
- 1. A high power MOS semiconductor device comprising, in combination, a semiconductor substrate, spaced source and drain regions of one conductivity type located in said semiconductor substrate, substantially V-shaped channel region having a region thereof of opposite conductivity type connected to said source region and to said drain region and providing a groove in said semiconductor substrate, a first insulating layer located in said groove in said semiconductor substrate and on said substantially V-shaped channel region, a doped electrically conductive polysilicon gate electrode layer located in said groove and on said first insulating layer, a second insulating layer located on and covering said polysilicon gate electrode layer, a first electrode electrically connected to one of said source and drain regions, and a second electrode electrically connected to the other of said source and drain regions, one of said first and second electrodes being located on said second insulating layer and covering substantially the entire surface area over one surface of said semiconductor substrate.
- 7. A high power MOS semiconductor device comprising, in combination, a semiconductor substrate, spaced source and drain regions of one conductivity type located in said semiconductor substrate, a pair of spaced substantially V-shaped channel regions, each of said pair of spaced substantially V-shaped channel regions having a region thereof of opposite conductivity type connected to said source region and to said drain region and providing a groove in said semiconductor substrate, a first insulating layer located in each groove in said semiconductor substrate and on each of said pair of spaced substantially V-shaped channel regions, a second insulating layer located in each groove and on said first insulating layer, a doped electrically conductive polysilicon gate electrode layer located in each said groove and on said second insulating layer, a third insulating layer located on and covering said polysilicon gate electrode layer, a first electrode electrically connected to one of said source and drain regions, and a second electrode electrically connected to the other of said source and drain regions, one of said first and second electrodes being located on said third insulating layer and covering substantially the entire surface area over one surface of said semiconductor substrate.
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14. A VMOS semiconductor device comprising, in combination, a semiconductor substrate region, spaced source and drain regions of one conductivity type located in said semiconductor substrate region, substantially V-shaped channel region having a region thereof of opposite conductivity type connected to said source region and to said drain region and providing a groove in said semiconductor substrate region, at least one insulating layer located in said groove in said semiconductor substrate region and on said substantially V-shaped channel region, a doped electrically conductive polysilicon gate electrode layer located in said groove and on said insulating layer, another insulating layer located on and covering said polysilicon gate electrode layer, a first electrode electrically connected to one of said source and drain regions, and a second electrode electrically connected to the other of said source and drain regions, one of said first and second electrodes being located on said another insulating layer.
Specification