Video processing system

• US 4,148,070 A
• Filed: 01/31/1977
• Issued: 04/03/1979
• Est. Priority Date: 01/30/1976
• Status: Expired due to Term

• Current Assignee: Quantel Limited 37 Victoria Avenue Southend On Sea Essex
• Original Assignee: Micro Consultants Ltd. (Belden Inc.)
• Inventors: Taylor, Richard J.
• Primary Examiner(s): Britton, Howard W.
• Application Number:
  US05/764,317
• Time in Patent Office: 792 Days
• Field of Search: 358/160, 358/140, 358/903, 358/905, 358/187, 358/105, 358/8, 358/141
• US Class Current: 348/719
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A video processing system comprises an analogue to digital converter for receiving a video signal and converting the signal into digital form. A digital frame store receives and stores the converted video data. Store addressing means address locations within the frame store to write in and read out data therefrom. A digital to analogue converter receives the data read out from the frame store and converts the data into analogue form and accessing means provides random access to the frame store locations during the video blanking time to allow processing of the data with an algorithm.

Claims

1. A video processing system comprising:

(a) analogue to digital converter means for receiving a video signal and converting said signal into digital form;

(b) a digital frame store for receiving and storing the converted video data;

(c) store addressing means for addressing locations within the frame store to write in and read out data therefrom;

(d) digital to analogue converter means for receiving data read out from said frame store and for converting the data into analogue form; and

(e) accessing means for providing random access to the frame store locations during the video blanking time to allow processing of the data with an algorithm so as to modify the data held at the accessed location in the store.

2. A video processing system according to claim 1 wherein the frame store includes control means for controlling the writing in and reading out of data from the store at the locations specified by the store addressing means, and read and write sequence generator means for sequencing of the store addressing means.

3. A video processing system comprising:

analogue to digital converter means for receiving a video signal and converting said signal into digital form;

a digital frame store for receiving and storing the converted video data;

store addressing means for addressing locations within the frame store to write in and read out data therefrom;

digital to analogue converter means for receiving data read out from said frame store and for converting the data into analogue form;

accessing means for providing random access to the frame store locations during the video blanking time to allow processing of the data with an algorithm so as to modify the data held at the accessed location in the store;

control means for controlling the writing in and reading out of data from the store at the locations specified by the store addressing means;

and read and write sequence generator means for sequencing of the store addressing means, and wherein the accessing means comprises;

a computer for generating the required address location information;

computer address means for receiving the address information and for applying the required addresses to the store addressing means;

computer buffer means for receiving data read from said frame store or data to be written into said frame store;

and computer sequencing means for providing timing signals for the computer address means and said computer buffer means to ensure that the data contained within the computer buffer means is only read from or written into the store during the line blanking interval.

4. A video processing system according to claim 3 wherein the computer buffer means receives read and write enabling signals from the read and write sequence generator means.

5. A video processing system according to claim 3 wherein the computer buffer means comprises a bi-directional store which receives and transmits data from and to the computer at a first rate compatible with the computer and which receives and transmits data from and to the frame store during the line blanking time at a second rate compatable with the frame store.

6. A video processing system according to claim 3 including a video input processor provided between the analogue to digital converter means and the frame store for controlling the amount of data written into the store from the analogue to digital converter means.

7. A video processing system according to claim 4 including video outputing means provided between the frame store and the digital to analogue converter means for controlling the amount of data converted by the digital to analogue converter means from the frame store data.

8. A video processing system according to claim 7 wherein control data storage means are provided which receives and stores control data from said computer to effect control of the processing of the data through said video input processor and said video outputing means.

9. A video processing system according to claim 8 wherein control data within the control data storage means is transmitted to the video input processor in response to an input update signal provided once a frame by the write sequence generator means, and wherein control data is transmitted to the video outputing means in response to an output update signal provided once a frame by the read sequence generator means.

10. A video processing system according to claim 8 wherein the store addressing means receives control data from the control data storage means to control the addressing of the frame store.

11. A video processing system according to claim 8 wherein the video outputing means receives control data from the control data storage means for modifying the data read out from the frame store.