Polling and data communication system having a pulse position to binary address conversion circuit

• US 4,149,144 A
• Filed: 07/05/1977
• Issued: 04/10/1979
• Est. Priority Date: 09/14/1976
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Diefenderfer, Charles G.
• Primary Examiner(s): Yusko, Donald J.
• Application Number:
  US05/812,692
• Time in Patent Office: 644 Days
• Field of Search: 340/147 R, 340/151, 340/152, 340/167 R, 340/168 R, 340/167 B, 179/15 AL, 178/2 R, 178/2 C, 178/2 D
• US Class Current: 370/255
• CPC Class Codes: G08C 15/12 the signals being represented by pulse characteristics in transmission link
• CPC Class Codes: H04Q 9/14 Calling by using pulses

Abstract

A poll command is sent by a central station to a plurality of remote stations connected along a data highway system. Upon receipt of the poll command, a remote station which desires to transmit data to the central station, responds with a reply pulse in a specific time position following the poll command. The position of the reply pulse is measured relative to the end of the poll command from the central station. Upon transmission of the poll command by the central station, a counter is started at the central station to count clock pulses arranged to occur at the end of each possible reply pulse position. Upon receipt of a reply pulse from a remote station, the count in the counter, which represents the binary address of the replying station, is stored in a memory and a memory address counter is incremented to control the storing of successive binary addresses in consecutive memory locations.

Claims

1. A pulse position to binary address converter for converting a physical position of a remote station on a data highway to a binary address for addressing the remote station comprising

a bidirectional data highway,

a plurality of remote stations connected to said data highway at spaced locations thereon, said remote stations each including means responsive to a poll command on said data highway for issuing a reply signal to a predetermined time following a reception of said poll command corresponding to the physical location for each of said remote stations,

controller means for issuing a poll command onto said data highway,

clock signal generating means,

bit counter means arranged to count clock signals from said clock signal generating means,

memory means connected to said counter means and

address counter means connected to said memory means to address storage locations in said memory means, said controller means being responsive to said reply signal from each of said remote stations to produce a corresponding transfer control signal which is applied to said memory means for enabling said memory means to transfer the count stored in said bit counter means at the time of the application of said transfer control signal to said memory means to a memory location as determined by a count stored in said address counter means and circuit means for applying each of said transfer control signals to said address counter means to increment the count stored in said address counter means following each transfer of a count from said bit counter to said memory means whereby each stored count in said memory means is a binary address of a corresponding remote station.

2. A pulse position to binary address converter as set forth in claim 1 and including a multiplexer circuit connected to said memory means for receiving stored count signals from storage locations in said memory means and for transferring said stored count signals to a multiplexer output line and circuit means connecting said multiplexer output line to said controller means to enable said controller means to apply said output signal on said multiplexer output line to said data highway to address a remote station connected to said data highway.

3. A converter as set forth in claim 1 wherein said means responsive to a poll command each include a signal detector connected to said data highway for detecting the poll command to produce a corresponding output signal and adjustable signal delay means connected between said signal detector and said data highway for applying said output signal to said data highway as said reply signal after a predetermined delay time.

4. A converter as set forth in claim 1 wherein said remote stations are each arranged to respond during a corresponding time window following the poll command with the number of time windows being at least equal to the number of remote stations and the clock signal generating means is arranged to produce a clock signal for each of the time windows.

5. A data communication system for converting a relative position of a remote station on a data highway to a binary address for addressing the remote station comprising

a bidirectional data highway,

a plurality of remote stations connected to said data highway at spaced locations thereon, said remote stations each including means responsive to a poll command on said data highway for issuing a reply signal at a predetermined time following said poll command corresponding to the relative position on said data highway for each of said remote stations,

controller means for issuing a poll command onto said data highway,

clock signal generating means,

bit counter means arranged to counter clock signals from said clock signal generating means,

memory means connected to said counter means and to said controller means,

address counter means connected to said memory means to address storage locations in said memory means, said controller means being responsive to said reply signal from each of said remote stations to produce a corresponding transfer control signal which is applied to said memory means to transfer the count stored in said bit counter means at the time of the application of said transfer control signal to said memory means to a memory location as determined by a count stored in said address counter means and

circuit means for applying each of said transfer control signals to said address counter means to increment the count stored in said address counter means following each transfer of a count from said bit counter to said memory means whereby each stored count in said memory means is a binary address of a corresponding remote station.

6. A data communication system as set forth in claim 5 and including a multiplexer circuit connected to said memory means for receiving stored count signals from storage locations in said memory means and for transferring said stored count signals to a multiplexer output line and circuit means connecting said multiplexer output line to said controller means to enable said controller means to apply said output signal on said multiplexer output line to said data highway to address a remote station connected to said data highway.

7. A data communication system as set forth in claim 5 wherein said means responsive to a poll command each include a signal detector connected to said data highway for detecting the poll command to produce a corresponding output signal and adjustable signal delay means connected between said signal detector and said data highway for applying said output signal to said data highway as said reply signal after a predetermined delay time.

8. A data communication system as set forth in claim 5 wherein said remote stations are each arranged to respond during a corresponding time window following the poll command with the number of time windows being at least equal to the number of remote stations and the clock signal generating means is arranged to produce a clock signal for each of the time windows.

9. A data communication system for converting a relative position of a remote station on a data highway to a binary address for addressing the remote station comprising

a bidirectional data highway,

controller means connected to said data highway for issuing a poll command onto said data highway,

a plurality of remote stations connected to said data highway, said remote stations each including means responsive to said poll command on said data highway for selectively issuing a reply signal at a predetermined time following a reception of said poll command corresponding to the relative position on said data highway for each of said remote stations, and

address generating means connected to said controller means for converting each time duration between said poll command and each of said reply signals from said remote stations to corresponding addresses for each of said remote stations issuing said reply signal.

10. A data communication system as set forth in claim 9 wherein said address generating means includes memory means for storing each of said addresses.

11. A data communication system as set forth in claim 10 wherein said memory means includes memory address means for storing each of said addresses in consecutive memory locations.

12. A method of converting a plurality of remote station relative positions on a data highway to separate binary addresses comprising the steps of issuing a command on the data highway to the remote stations, starting a counting by a counter of the output signals from a clock source following the end of said command, effecting a reply signal on the data highway from each remote station to said command at a time following a reception of said command corresponding to a relative position of each of said remote stations on said data highway, transferring the count stored in the counter to a memory upon the occurrence of a reply pulse from the remote station and concurrently incremeting a memory address register to store successive counts from the counter in consecutive memory locations.

13. A method as set forth in claim 12 and including the further step of sequentially reading the consecutive memory locations in said memory to obtain respective addresses for said remote stations.

14. A method as set forth in claim 12 wherein said reply signals are effected in a time sequence corresponding to the physical sequence of said remote stations on said data highway.

15. A method as set forth in claim 12 wherein said reply signals are each arranged to issue during a respective time window with the number of time windows corresponding with the number of remote stations.

16. A method as set forth in claim 15 wherein each of said output signals from said clock source is arranged to occur during a respective one of the time windows.

17. A method as set forth in claim 16 wherein each of said reply signals is arranged to occur in a time window corresponding to the physical sequence of a respective one of said remote stations on said data highway.

18. A method of converting a plurality of remote station relative positions on a data highway to separate respective binary addresses comprising the steps of issuing a command on the data highway to the remote stations, selectively effecting a reply signal on the data highway from each remote station to said command at a time following a reception of said command corresponding to a relative position of each of said remote stations on said data highway;

and converting each time duration between said command and each of said reply signals from said remote stations to corresponding addresses for each of said remote stations issuing said reply signal.

19. A method as set forth in claim 18 and including the further step of storing said addresses in a memory.

20. A method as set forth in claim 19 wherein said addresses are stored in consecutive memory locations in said memory.

21. A method as set forth in claim 20 and including the further step of sequentially reading the consecutive memory locations in said memory to obtain respective addresses for said remote stations issuing said reply signal.