Signature encoding for integrated circuits

• US 4,150,331 A
• Filed: 07/29/1977
• Issued: 04/17/1979
• Est. Priority Date: 07/29/1977
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Burroughs Incorporated (Terreno Realty Corp.)
• Inventors: Lacher, William A.
• Primary Examiner(s): Krawczewicz, Stanley T.
• Application Number:
  US05/820,233
• Time in Patent Office: 627 Days
• Field of Search: 324/73 PC, 324/73 R, 324/158 R, 324/158 D, 324/51
• US Class Current: 324/133
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 2201/83 the solution involving signatures

Abstract

The present disclosure describes an improved integrated circuit chip which includes in addition to the logic circuits for performing its design function, an additional circuit for providing a unique reference pattern in digital form useful for test purposes. This reference pattern is automatically read by the tester and gives information as to the type of chip and its final signature. The former indicates to the tester an appropriate test routine such as a pseudo-random binary sequence; and the latter, the predetermined digital pattern which will be present on all of the input and output terminals of a properly functioning integrated circuit chip at the conclusion of the test. Since each chip signature is read by the tester itself, no reference to signatures customarily recorded in tables or inscribed on circuit schematics is required by the test technician.

Claims

1. In an integrated circuit chip having circuit means for performing a logic function and a plurality of input/output terminals upon which the logic levels associated with said function appear, the improvement comprising:

additional circuit means formed within said chip and being independent of said circuit means for performing said logic function, said additional circuit means being coupled to predetermined ones of said input/output terminals for encoding a fixed unalterable digital reference pattern within said chip.

2. An integrated circuit chip as defined in claim 1 characterized in that said digital reference pattern is comprised of a plurality of signal levels appearing respectively on said input/output terminals in response to the interrogation thereof.

3. An integrated circuit chip as defined in claim 2 further characterized in that said digital reference pattern includes a chip signature, said chip signature being chosen to correspond to the signal levels appearing respectively on a first selected group of said input/output terminals at the conclusion of a predetermined test sequence applied to said chip, said last-mentioned signal levels being indicative of the satisfactory performance by said chip of said logic function.

4. An integrated circuit chip as defined in claim 3 further characterized in that said digital reference pattern includes in addition to said chip signature, data as to the "type" of chip, said data appearing as signal levels on a respective second selected group of said input/output terminals and being useful in the predetermination of said test sequence applied to said chip.

5. In a test system including an integrated circuit chip having circuit means for performing a logic function, said chip comprising:

a plurality of input/output pins associated with said logic function and at least one additional test pin,

additional circuit means formed within said chip for encoding a predetermined fixed digital reference pattern therein, said additional circuit means being independent of said circuit means for performing said logic function,

said additional circuit means comprising a plurality of unidirectional current conducting devices, each device having at least first and second electrodes, the first electrodes of said devices being connected respectively to selected ones of said input/output pins in accordance with said predetermined reference pattern, the second electrodes of said devices being connected to a common bus, said bus being connected to said test pin,

the connection of a unidirectional current conducting device to a given one of said selected pins being indicative of a first binary state associated with said given pin and the absence of said device at another non-selected pin being indicative of a second binary state associated therewith, the respective binary states present on said input/output pins and the signal levels corresponding respectively thereto defining said predetermined fixed digital reference pattern.

6. A system as defined in claim 5 wherein said unidirectional current conducting devices are diodes, the anode of each diode being connected to one of said selected input/output pins and the cathodes of all of said plurality of diodes being connected to said common bus.

7. A system as defined in claim 6 further including within said chip a pair of protective series connected diodes, the anode of a first of said protective diodes being connected to ground potential and its cathode being connected to the anode of a second of said protective diodes, the cathode of said second diode being connected to said common bus.

8. A system as defined in claim 7 wherein said chip further includes test and diagnostic circuits coupled to said test pin.

9. A system as defined in claim 5 further characterized in that a portion of said reference pattern derived from first chosen ones of said input/output pins defines a chip signature selected to correspond to the signal levels present on the respective latter pins of a properly functioning chip at the conclusion of a predetermined test sequence applied to said chip for ascertaining the integrity of the logic function performed thereby.

10. A system as defined in claim 5 further including means for interrogating each input/output pin to ascertain the binary state associated therewith.

11. A system as defined in claim 10 further characterized in that said means for interrogating each input/output pin comprises means for applying a current sink to said test pin and concurrently sequentially applying a voltage potential to each input/output pin, the voltage levels appearing serially on said test pin as a result of said sequential interrogation of said input/output pins being representative of the respective binary states associated with said pins and corresponding to said reference pattern.

12. A system as defined in claim 9 further characterized in that another portion of said reference pattern derived from second chosen ones of said input/output pins defines the "type" of said integrated circuit chip.