Trim network for monolithic circuits and use in trimming a d/a converter

• US 4,150,366 A
• Filed: 09/01/1976
• Issued: 04/17/1979
• Est. Priority Date: 09/01/1976
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Price, John J.
• Primary Examiner(s): Sloyan, Thomas J.
• Application Number:
  US05/719,549
• Time in Patent Office: 958 Days
• Field of Search: 338/195, 340/347 DA, 340/347 CC
• US Class Current: 341/121
• CPC Class Codes: H01C 17/23 by opening or closing resistor geometric tracks of predetermined resistive values, e.g. snapistors
• CPC Class Codes: H03M 1/0646 by analogue redistribution among corresponding nodes of adjacent cells, e.g. using an impedance network connected among all comparator outputs in a flash converter
• CPC Class Codes: H03M 1/1057 by trimming, i.e. by individually adjusting at least part of the quantisation value generators or stages to their nominal values
• CPC Class Codes: H03M 1/785 using resistors, i.e. R-2R ladders

Abstract

There is disclosed a trim network suitable to be utilized in monolithic circuits and a method of trimming thereof to improve performance of the circuits to achieve greater yields. The network comprises at least one monolithic resistor connected across a known voltage potential and including a plurality of contacts thereon defining incremental resistances therebetween. The contacts are coupled to a common terminal via a plurality of metallic links. A desired output voltage is derived at the common terminal by open circuiting all of the links but a desired one. The voltage appearing at the common terminal can then be used for trimming a parameter of the monolithic circuit to improve the performance thereof.

Claims

1. In a digital-to-analog converter circuit including a reference circuit for providing a reference voltage, a plurality of subsequent least significant input bit terminals adapted to receive a digital input signal, an untrimmed resistive ladder for dividing the reference current into binary related currents having ideal values associated therewith and a plurality of termination amplifiers corresponding to each input bit terminal for providing a low impedance termination to respective rungs of the resistive ladder, the improvement comprising a trim network coupled to the termination amplifiers for adjusting the currents through each rung of the untrimmed resistive ladder such that the value of the binary related currents are substantially equal to the ideal values thereby improving the linearity of the converter circuit, said trim network including at least one impedance means being coupled between a predetermined potential when the digital to analog converter is in an operative state and a plurality of alterable conductor means coupled with said at least one impedance means and a respective one of the termination amplifiers whereby predetermined incremental resistance values are defined between each pair of said plurality of alterable conductor means to define a predetermined difference voltage therebetween such that a predetermined voltage is supplied to said respective termination amplifier when all but a selected one of said conductive means are open circuited by thermal machining.

2. The circuit of claim 1 wherein said one impedance means includes:

resistive means connected across first and second predetermined potentials and having a plurality of contacts disposed thereon;

said alterable conductor means being a plurality of metallic links each having one end thereof connected to a common terminal and the other end connected to respective ones of said contacts disposed on said resistive means;

circuit means coupling said common terminal of said metallic links to said respective termination amplifier such that the voltage appearing at said common terminal is caused to be varied to adjust the value of the current through an associated rung of the ladder.

3. The circuit of claim 2 wherein said impedance means includes a plurality of said resistive means, each one of said resistive means being coupled to a respective termination amplifier for adjusting the current through respective rungs of the ladder to have a value substantially equal to the ideal values.

4. A monolithic digital-to-analog converter comprising in combination:

an output terminal adapted to be coupled to a load;

input circuit means adapted to receive an input signal for deriving a reference current;

impedance means responsive to said reference current for dividing the same into desired individual weighted currents, said impedance means requiring trimming thereof to cause the actual weighted currents to have values substantially equal to said desired values;

termination means for providing low impedance terminations to said impedance means and to provide a predetermined potential thereto;

current switching means adapted to receive a digital input signal for either steering currents to said termination means from said output terminal or from a power supply terminal to derive an analog output signal representative of said digital input signal; and

trimming means coupled to said termination means including at least one resistive means and a plurality of alterable conductor means incrementally coupled to said resistor means for defining incremental resistance values therebetween, said plurality of conductor means being interconnected at a common terminal such that an adjustable and known potential is provided at said common terminal by selectively open circuiting all but one of said conductor means whereby the actual weighted currents through said impedance means are substantially equal to said desired currents.

5. The digital-to-analog converter of claim 4 wherein:

said impedance means includes a resistive ladder having a plurality of individual bit current rungs;

said termination means includes a plurality of amplifier means each coupled to respective ones of said bit current rungs of said resistive ladder; and

said at least one resistive means includes a plurality of contacts thereon for defining said incremental resistances therebetween and said alterable regions being a plurality of metallic links each having an end thereof connected to respective contacts and the other end thereof connected to said output of said trimming means at said common terminal, all of said links being open-circuit but one to derive said predetermined potential.

6. The converter of claim 5 wherein said trimming means includes a plurality of said resistive means for adjusting the current flow through respective ones of said rungs of said resistive ladder.

7. The converter of claim 5 wherein said trimming means is spatially separated from said impedance means a sufficient distance to allow thermal machining thereof to open-circuit said links.

8. In an integrated circuit having a first impedance network for establishing a plurality of weighted currents having desired values, a trim circuit for providing passive trimming of the integrated circuit comprising second impedance means being spatially separated from the first network to allow thermal machining thereat and electrically coupled to the first impedance network for adjusting the weighted currents to be substantially the desired values, said trim circuit including;

(a) at least one resistive means connected between a first and second potential, said resistive means having a plurality of contacts defining incremental resistances therebetween; and

(b) a plurality of metallic links each having an end thereof connected to respective contacts of said resistive means with the other end of each of said links being coupled to a common terminal such that a predetermined and adjustable voltage is derived at said common terminal when all but a predetermined one of said links are open-circuited when the integrated circuit is in a passive state by said thermal machining said predetermined voltage being applied to said first impedance network such that the weighted currents are adjusted to the desired values.

9. The trim circuit of claim 8 wherein said resistive means includes a monolithic resistor.

10. A trim network for adjusting the magnitude of current through a resistive load, comprising:

at least one resistive element connected across a known voltage potential which includes a plurality of contacts defining incremental resistances therebetween such that a plurality of incremental voltage potentials are developed at each contact respectively.

a plurality of metallic links having one end thereof connected to a common terminal with the other ends of each link being connected to respective ones of said contacts, each one of said metallic links being open-circuited except a predetermined one such that a predetermined potential is developed at said common terminal, said predetermined potential being varied in accordance to which links are open-circuited; and

circuit means electrically coupled between said common terminal and the resistive load for causing the voltage across the load to vary as said potential at said common terminal is caused to vary to thereby cause the current through said load to be adjusted.

11. The network of claim 10 wherein said resistive element includes a monolithic resistor.

12. The network of claim 11 wherein said circuit means includes a termination amplifier for providing a low impedance termination to the resistive load.

13. In a monolithic integrated circuit including at least one circuit portion, a network for providing passive trimming of predetermined circuit parameters of the circuit portion, comprising:

impedance means being coupled between a predetermined fixed potential produced by the monolithic integrated circuit when the monolithic integrated circuit is in an operative state;

a plurality of conductive links each attached at one end thereof to said impedance means such that an incremental impedance is produced between successive ones of said plurality of conductive links, the other end of each one of said plurality of conductive links being commonly connected, all but one of said plurality of conductive links being open-circuited by thermal machining thereof when the monolithic integrated circuit is in a nonoperative state such that a predetermined voltage is produced at said commonly connected ends of said plurality of conductive links when the monolithic integrated circuit is in an operative state; and

circuit means for coupling said commonly connected ends of said plurality of conductive links to the at least one circuit portion of the monolithic integrated circuit such that the circuit parameters thereof are adjusted to the desired predetermined values by said predetermined voltage being applied thereto.

14. The network of claim 13 wherein said impedance means is a monolithic resistor.

15. The network of claim 14 wherein each one of said plurality of conductive links being formed of aluminum material compatible with monolithic integrated circuit process techniques.

16. In a monolithic integrated circuit including a resistive circuit for producing a weighted current of desired value when the monolithic integrated circuit is in an operative state, a network suitable for providing passive timming of the monolithic integrated circuit, comprising:

first power supply conductor means;

second power supply conductor means, said first and second power supply conductor means having a predetermined and fixed voltage appearing thereacross when the monolithic integrated circuit is in an operative state;

resistive means being coupled between said first and second power supply conductors and having a plurality of contacts formed thereon which define incremental resistances therebetween;

a plurality of metallic links each having one end thereof connected to a respective one of said plurality of said contacts formed on said resistive means, the other ends of said plurality of metallic links being connected to a common terminal;

circuit means for coupling said common terminal to the resistive circuit of the monolithic integrated circuit; and

all but one of said plurality of metallic links being selectively open circuited when the monolithic integrated circuit is in a nonoperative state such that a predetermined voltage is produced at said common terminal when the monolithic integrated circuit is in an operative state whereby the current produced in the resistive circuit of the monolithic integrated circuit is adjusted to the desired value.