Text editing and display system having a multiplexer circuit interconnecting plural visual displays

• US 4,150,429 A
• Filed: 07/30/1976
• Issued: 04/17/1979
• Est. Priority Date: 09/23/1974
• Status: Expired due to Term

• Current Assignee: Atex Publishing Systems Corp. (Eastman Kodak Company)
• Original Assignee: Atex, Inc. (Naviga Inc.)
• Inventors: Ying, Charles W.
• Primary Examiner(s): Springborn, Harvey E.
• Application Number:
  US05/710,220
• Time in Patent Office: 991 Days
• Field of Search: 364/200 MS File
• US Class Current: 710/316
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/38 Information transfer, e.g. on bus G06F13/14 takes precedence
• CPC Class Codes: G06F 3/153 using cathode-ray tubes

Abstract

A text-editing system includes a central processor unit, a bus connected to the central processor unit and input terminals connected to the bus for entering text and editing commands into the system. Text is displayed by the system on visual display apparatuses that are associated with each input terminal based upon information that is stored in display memories. A multiplexer circuit connects plural visual display apparatuses to the bus and a display memory and routes address and data signals between the display memory and either the bus or selected ones of the visual display apparatuses.

Claims

1. An electronic text-editing system comprising:

A. editing means including a central processor unit for performing text-editing functions,

B. a plurality of editing stations each having an input terminals for entering text to be edited into said editing means and for entering editing commands that control the editing functions performed by said editing means,

C. a common bus interconnecting said editing means and said plurality of input terminals, said common bus including data signal, address signal and transfer control signal conductors, and

D. a plurality of display assemblies connected to said common bus, each said display assembly comprising;

i. a memory for storing data representing text to be edited, said memory having address signal, data signal and transfer control conductors and including a plurality of addressable storage locations, each said storage location being identified by a unique set of address signals on said common bus address signal conductors,

ii. a plurality of visual display means, each visual display means having address signal, data signal and transfer control signal conductors and each said visual display means constituting an output terminal and being connected for operation with a said display device of said editing station at which text entered at said input terminal is routed by said editing means from said input terminal over said common bus to said memory for a visual presentation by said visual display device, and

iii. multiplexing means connected to said common bus, said memory and each said visual display, means, said multiplexing means including;

a. controllable data switching means interconnecting all of said data signal conductors for routing data signals between said common bus and said memory and between said visual display means and said memory,

b. controllable address switching means interconnecting all of said address signal conductors for routing address signals from said common bus to said memory and from said visual display means to said memory, and

c. transfer control means connected to said controllable data switching means and said controllable address switching means for interconnecting all said transfer control signal conductors, said transfer control means including means responsive to said transfer control signals for generating a switching control signal that controls the routing of address and data signals by said controllable address switching means and said controllable data switching means, respectively.

2. An electronic text-editing system as recited in claim 1 wherein each said multiplexing means further includes:

d. memory address decoder means connected to said common bus address signal conductors and said transfer control means for generating a bus selection signal in response to address signals from said common bus that correspond to an address for said memory, and

e. display address decoder means connected to said address signal conductors for said visual display means and said common bus for establishing a data transfer path between each said visual display means and said common bus in response to address signals from said common bus that designate said visual display means.

3. An electronic text-editing system as recited in claim 2 wherein the switching control signal assumes first and second states and said controllable data switching means comprises:

i. first connection means connected to said common bus data signal conductors,

ii. second connection means connected to said memory data signal conductors,

iii. third connection means connected to said visual display means data signal conductors, and

iv. a controllable switching circuit connected to said first, second and third connection means and responsive to a first state of the switching control signal for interconnecting said first and second connection means and to the second state of the switching control signal for interconnecting said second and third connection means.

4. An electronic text-editing system as recited in claim 2 wherein each said multiplexing means includes priority arbitration means connected to the transfer control conductors of said common bus and of said visual display means for selecting said common bus or one of said visual display means for operation during a transfer of data signals with said memory.

5. An electronic text-editing system as recited in claim 2 wherein said memory responds to address signals corresponding to said memory and a first transfer control signal for producing a data transfer over said data signal conductor and for generating a second transfer control signal and wherein said transfer control means includes:

i. a bistable element characterized by having set and cleared states;

ii. means connected to said transfer control signal conductors of said common bus and said visual display means, for changing the state of said bistable element,

iii. a first gate connected to said bistable element and said memory, said first gate being energized when said bistable element assumes the set condition and said memory generates the second transfer control signal,

iv. a second gate connected to said first gate and to said transfer control means, said second gate being energized when said first gate is energized and the switching control signal is active for transmitting to said common bus another transfer control signal acknowledging the completion of a data transfer, and

v. a third gate connected to said first gate and said transfer control means, said third gate being enabled by said first gate in response to a transfer control signal from a said visual display means for generating a signal indicating the availability of data on said memory data signal conductors and for causing said visual display means to transfer the data thereto.