High density N-channel silicon gate read only memory

• US 4,151,020 A
• Filed: 01/26/1977
• Issued: 04/24/1979
• Est. Priority Date: 01/26/1977
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: McElroy, David J.
• Primary Examiner(s): Ozaki, G.
• Application Number:
  US05/762,612
• Time in Patent Office: 818 Days
• Field of Search: 357/45, 148/187, 148/188, 148/1.5, 29/569 L, 29/577 R, 29/577 C
• US Class Current: 438/275
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/367 Gate dielectric programmed, e.g. different thickness

Abstract

An N-channel silicon gate read only memory or ROM array of very high bit density is made by providing columns in the form of parallel N+ moats separated by field oxide and removing small areas of the field oxide in a pattern of "1'"'"'s" and "0'"'"'s" according to the ROM program. Gate oxide is grown in the areas where field oxide is removed, and parallel polycrystalline silicon strips are laid down over the field oxide and gate oxide areas normal to the moats, providing the rows. The ROM may be made as part of a standard double level poly, N-channel, self-aligned silicon gate process. The columns may include an output line and several intermediate lines for each ground line so that a virtual ground format is provided. An implant step may be used to avoid the effects of exposed gate oxide so that zero-overlap design rules are permitted.

Claims

1. A method of making a semiconductor device comprising the steps of masking a plurality of parallel elongated regions of a face of a semiconductor body against oxidation, growing thick field oxide in the spaces between the elongated regions but not above the elongated regions, removing small areas of the field oxide in a pattern according to where functioning transistors are to be created, forming thin gate dielectric in said small areas, and applying a plurality of parallel elongated conductive strips over the field oxide and gate dielectric in a direction normal to the elongated regions.

2. A method according to claim 1 wherein the semiconductor device is a read only memory and the field oxide is removed in a pattern of logic "1'"'"'s" and "0'"'"'s."

3. A method according to claim 2 wherein the semiconductor body is P-type silicon, the conductive strips are doped polycrystalline silicon, and the transistors are of the N-channel silicon gate type.

4. A method according to claim 3 wherein the elongated regions become N+ moats.

5. A method according to claim 4 wherein the field oxide is many times thicker than the gate dielectric.

6. A method of making a semiconductor device comprising the steps of:

masking a plurality of elongated parallel areas on a face of a semiconductor wafer with a material which inhibits oxidation;

growing a thick field oxide on said face while leaving unoxidized a plurality of elongted parallel regions;

removing the masking material;

introducing a conductivity type determining impurity into said face of said semiconductor wafer to heavily-dope the plurality of elongated regions;

selectively removing the thick field oxide in areas between a plurality of the elongated regions;

growing thin gate oxide in such areas; and

providing a plurality of strips of conductive material over the field oxide generally perpendicular to the elongated regions extending across the plurality of areas.

7. A method according to claim 6 wherein the conductive material is doped polycrystalline silicon.

8. A method according to claim 7 wherein N-channel silicon gate MOS transistors are created at said plurality of areas.

9. A method according to claim 7 wherein the semiconductor device is a read only memory and the steps of selectively removing the thick field oxide programs the memory in a pattern of logic ones and zeros.

10. A method according to claim 7 wherein a silicon gate MOS transistors ae created at said selected areas.

12. A method according to claim 6 wherein the conductive material is polycrystalline silicon.

11. A method of making an N-channel read only memory comprising the steps of:

masking a plurality of elongated parallel areas on a face of a semiconductor body with a material which inhibits oxidationl;

growing a thick field oxide on said face while leaving unoxidized a plurality of elongated parallel regions at said parallel areas;

removing the masking material;

introducing a conductivity type determining impurity into said face of the semiconductor body to heavily dope the plurality of elongated regions;

selectively removing the thick field oxide in selected areas between a plurality of the elongated regions while leaving other such areas of field oxide intact to program the memory in a pattern of logic ones and zeros;

forming thin gate dielectric in the selected areas; and

providing a plurality of strips of conductive material over the field oxide generally perpendicular to the elongated regions extending across the selected areas.