Closed loop companding ratio control for continuously variable slope delta modulation

• US 4,151,517 A
• Filed: 02/14/1977
• Issued: 04/24/1979
• Est. Priority Date: 02/14/1977
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Kelley, Stephen H.
• Primary Examiner(s): Miller, Charles D.
• Application Number:
  US05/768,117
• Time in Patent Office: 799 Days
• Field of Search: 340/347 C, 340/347 AD, 325/38 B, 332/11 D
• US Class Current: 341/108
• CPC Class Codes: H03M 3/024 using syllabic companding, e.g. continuously variable slope delta modulation [CVSD]

Abstract

A monolithic integrated circuit encoder/decoder capable of converting an analog signal to a digital signal and capable of reconstructing an analog signal from a digital signal employing continuously variable slope delta modulation. The dynamic range of the continuous variable slope delta modulation is increased by employing means for providing a companding ratio reference coupled to a means for comparing the companding ratio reference against a filtered coincidence output from the encoder/decoder and then amplifying any difference therebetween. The difference is used to control the gain of the continuously variable slope delta modulator and can be used to modify the companding ratio reference to provide a closed-loop controlled companding ratio for the encoder/decoder.

Claims

1. A continuously variable slope delta modulation circuit for encoding/decoding input signals, comprising:

a comparator having a first input, a second input and an output, the first input being for receiving input information;

a sampler having a first and a second input and an output, the first input being adapted for receiving clock pulses, and the second input being coupled to the output of the comparator;

an integrator having an input and an output, the output being coupled to the second input of the comparator;

a slope polarity switch having a first input, a second input, and an output, the output being coupled to the input of the integrator, the first input of the slope polarity switch being coupled to the output of the sampler;

a level detect algorithm having an input and an output, the input being coupled to the output of the sampler;

a first amplifier having a first input, a second input, and an output, the first and second inputs forming a differential input, the first input of the first amplifier being coupled to the output of the level detect algorithm;

a companding ratio reference coupled to the second input of the first amplifier, the output of the first amplifier coupled to the second input of the slope polarity switch; and

a second amplifier having a first input, a second input, and an output, the output being coupled to the second input of the first amplifier, the first and second inputs forming a differential input, the first input being coupled to the output of the level detect algorithm, and the second input being coupled to the output of the first amplifier.

2. The circuit of claim 1 wherein the companding ratio reference includes a diode to provide a diode voltage drop for use as a reference voltage.

3. The circuit of claim 1 further including a filter coupled to the output of the level detect algorithm.

4. A continuously variable slope delta modulation circuit for encoding analog signals and decoding digital signals and having a non-linear slope magnitude controller for controlling an integrator within the circuit, comprising:

a means for receiving input data and adapted for receiving clock pulses to clock the data through the means for receiving;

means to monitor at least three bits of data from the means for receiving wherein the at least three bits correspond to the last bits of data out of the means for receiving, the means to monitor providing a coincidence output whenever all the bits being monitored are of an identical logic level;

a means to provide a difference signal coupled to the means to monitor;

a companding ratio reference coupled to the means to provide and providing a reference input to the means to provide so the means to provide can provide the difference signal;

means to couple the output of the means to provide to the companding ratio reference to provide a closed-loop controlled companding ratio reference;

a slope polarity switch having a first and a second input and an output;

the first input being coupled to the means for receiving and the second input being coupled to the output of the means to provide; and

an integrator coupled to the output of the slope polarity switch and providing an analog output reconstructed from an output of the means for receiving.

5. The continuously variable slope delta modulation circuit of claim 4 wherein the means to provide includes a low pass filter which is charged by the coincidence output.

6. The continuously variable slope delta modulation circuit of claim 5 wherein the means to provide further includes means to compare and amplify any difference between the coincidence output and the companding ratio reference.

7. A circuit having a continuously variable slope delta modulator for encoding an analog signal to produce a digital output signal, comprising:

a comparator for receiving the analog signal;

a sampler for sampling the analog signal at a rate established by a clock signal, the sampler being coupled to the comparator to receive an output from the comparator;

a logic level detector to produce a coincidence output when at least three successive logic bits from the sampler are of identical logic level value;

a slope magnitude controller coupled to the logic level detector to receive the coincidence output and to provide a companding ratio signal;

a companding ratio reference coupled to the slope magnitude controller for providing a reference to the magnitude controller;

means to couple an output from the slope magnitude controller to the companding ratio reference so that the output of the slope magnitude controller can modify the reference provided by the companding ratio reference thereby providing a non-linear closed-loop controlled companding ratio reference;

a slope polarity switch coupled to the magnitude controller and to an output of the sampler, the polarity switch being controlled by an output of the magnitude controller; and

an integrator coupled to the slope polarity switch for integrating an output from the slope polarity switch and for providing a controlling input to the comparator.

8. The circuit of claim 7 further including a low pass filter coupled between the logic level detector and the non-linear slope magnitude controller.

9. The circuit of claim 8 wherein the slope magnitude controller includes means for comparing an output from the low pass filter against an output from the companding ratio reference and amplifying any difference therebetween.

10. The circuit of claim 7 wherein the companding ratio reference includes a diode to provide a diode voltage drop for use as a reference voltage.

11. A monolithic integrated circuit encoder/decoder capable of converting an analog signal to a digital signal and capable of reconstructing an analog signal from a digital signal of the type including a delta modulation circuit and having an integrator, the improvement comprising:

means for providing a companding ratio reference; and

means for comparing the companding ratio reference against a filtered coincidence output from the encoder/decoder and amplifying any difference therebetween to provide gain control for the integrator wherein the means for comparing includes a first operational amplifier for comparing and amplifying and having an output coupled to the encoder/decoder, and a second operational amplifier for comparing the filtered coincidence output against the output of the first operational amplifier and providing an output coupled to the means for providing thereby being capable of overriding the companding ratio reference to provide a non-linear closed-loop companding ratio control for the encoder/decoder.

12. The encoder/decoder of claim 11 wherein the means for providing includes at least one diode drop to provide the companding ratio reference.

13. An encoder/decoder capable of converting an analog signal to a digital signal and converting a digital signal to an analog signal of the type having a delta modulator/demodulator, a logic level coincident detector, and a low pass filter wherein the improvement comprises a first amplifier having an inverting and a non-inverting input and an output, the inverting input being coupled to the low pass filter, the output being coupled to the delta modulator/demodulator;

means for providing a companding ratio reference and having an output coupled to the non-inverting input of the first amplifer; and

a second amplifier having an inverting and a non-inverting input and an output coupled to the output of the means for providing, the inverting input being coupled to the output of the first amplifier and the non-inverting input being coupled to the low pass filter so that the improvement provides a closed-loop controlled companding ratio.

14. The encoder/decoder of claim 13 wherein the means for providing the companding ratio reference has at least one diode to provide at least one diode voltage drop for the output which is coupled to the non-inverting input of the first amplifier.