Power supply control system for memory systems

• US 4,151,611 A
• Filed: 03/28/1977
• Issued: 04/24/1979
• Est. Priority Date: 03/26/1976
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Electric Co., Ltd. (Toshiba Corporation)
• Original Assignee: Tokyo Shibaura Electric Co., Ltd. (Toshiba Corporation)
• Inventors: Namimoto, Keiji, Sugawara, Mutsuo
• Primary Examiner(s): Konick, Bernard
• Assistant Examiner(s): McElheny, Jr., Donald
• Application Number:
  US05/782,081
• Time in Patent Office: 757 Days
• Field of Search: 340/173 R, 364/200 MS File, 364/900 MS File, 364/200, 364/900, 364/492, 364/707, 365/189, 365/230, 365/226, 365/227, 365/228, 365/229, 307/238
• US Class Current: 365/227
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 17/08 using semiconductor devices, e.g. bipolar elements G11C17/06, G11C17/14 take precedence
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

A power supply control system for memory systems includes a power control unit for controlling the power supply for read/write operation when data is read into MOS-IC memory chips. The power control unit is constructed in such a manner that necessary power supply voltage for read/write operation is supplied to the selected memory chip during the time period when the read/write operation is executed, while no power is supplied to the non-selected memory chips.

Claims

1. A memory system comprising:

a plurality of semiconductor chips each having address terminals to which an address signal is applied to designate a memory location therein, data terminals to which is applied a data signal which is written into the designated memory location or is read out of the designated memory location, a chip enable terminal to which is applied a chip enable signal during which a read operation or write operation is performed, memory content holding power supply terminal to which a power supply voltage is normally applied to hold memorized content of memory chips and a read/write power supply terminal to which a power supply voltage necessary for read/write operation is applied;

a power supply connected to the memory content holding power supply terminal of each of said memory chips;

bus means for transferring an address signal including a first part signal designating a memory location of said memory chips and a second part signal for selecting one of said memory chips;

processor means for producing first and second data transfer control signals each taking successively a first voltage level and a second voltage level and specifying a first memory addressing state in which the first and second control signals are at the first voltage level, a second read/write operation execution state in which one of the first and second control signals is at the first voltage level and the other is at the second voltage level and a third idle state in which the first and second control signals are at the second voltage level, said states following in succession during a read or write cycle;

means connected to said bus means and responsive to the first state of the first and second control signals to apply the first part signal of said address signal to the address terminals of each of said memory chips and responsive to the second state of the control signals to apply the chip enable signal and the read/write control signal respectively to the chip enable terminal and the read/write control terminal of each of said memory chips; and

means responsive to the first and second states of the first and second control signals and the second part signal of the address signal to couple said power supply to the read/write operation power supply terminal of a memory chip selected by the address signal only during the first and second states of the first and second control signals.

2. A memory system comprising;

a plurality of semiconductor memory chips each having address terminals to which an address signal is applied to designate a memory location therein, data terminals to which is applied a data signal which is written into the designated memory location or is read out of the designated memory location, a chip enable terminal to which is applied a chip enable signal during which a read operation or write operation is executed;

memory content holding power supply terminal to which a power supply voltage is normally applied to hold memorized contents of said memory chips and a read/write power supply terminal to which a power supply voltage necessary for read/write operation is applied;

a power supply connected to the memory content holding power supply terminal of each of said memory chips;

bus means for transferring an address signal including a first part signal designating a memory location of said memory chips and a second part signal for selecting one of said memory chips;

processor means for producing first and second data transfer control signals each taking successively a first voltage level and a second voltage level and specifying a first memory addressing state in which the first and second control signals are at the first voltage level, a second read/write operation execution state in which one of the first and second control signals is at the first voltage level and the other is at the second voltage level dependent on the read or write operation, and a third idle state in which the first and second control signals are at the second voltage level, said states following in succession during a read or write cycle;

means connected to said bus means and responsive to the first state of the first and second control signals to apply the first part signal of the address signal to the address terminals of each of said memory chips, and responsive to the second state of the control signals to apply the chip enable signal and the read/write control signal to the chip enable terminal and the read/write control terminal of each of said memory chips, respectively; and

means responsive to the second part signal of the address signal to couple said power supply to the read/write power supply terminal of a memory chip selected by the second part signal of the address signal during the first, second and third states of the control signals during a read or write cycle.

3. A memory system comprising:

a plurality of semiconductor memory chips each having address terminals to which an address signal is applied to designate a memory location therein, data terminals to which is applied a data signal which is written into the designated memory location or is read out of the designated memory location, a chip enable terminal to which is applied a chip enable signal during which a read operation or write operation is executed, a memory content holding power supply terminal to which a power supply voltage is normally applied to hold memorized contents of said memory chips and a read/write power supply terminal to which a power supply voltage necessary for read/write operation is applied;

a power supply connected to said memory content holding power supply terminal of each of said memory chips;

bus means for transferring an address signal including a first part signal designating a memory location of said memory chips and a second part signal for selecting one of said memory chips;

processor means for providing first and second data transfer control signals each taking successively a first voltage level and a second voltage level and specifying a first memory addressing state in which the first and second control signals are at the first voltages level, a second read/write operation execution state in which one of the first and second control signals is at the first voltage level and the other is at the second voltage level dependent on the read or write operation, and a third idle state in which the first and second control signals are at the second voltage level, said states following in succession during a read or write cycle;

means responsive to the first state of the first and second control signals to apply the first part signal of the address signal to said address terminals of each of said memory chips, responsive to the second state of the control signals and the second part signal of the address signal to apply the chip enable signal to said chip enable terminal of a memory chip selected by the second part signal of the address signal, and to the second state of the control signals to apply the read/write control signal to said read/write control terminal of each of said memory chips; and

means responsive to the first and second states of the first and second control signals to couple said power supply to said read/write power supply terminal of each of said memory chips.