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Power supply control system for memory systems

  • US 4,151,611 A
  • Filed: 03/28/1977
  • Issued: 04/24/1979
  • Est. Priority Date: 03/26/1976
  • Status: Expired due to Term
First Claim
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1. A memory system comprising:

  • a plurality of semiconductor chips each having address terminals to which an address signal is applied to designate a memory location therein, data terminals to which is applied a data signal which is written into the designated memory location or is read out of the designated memory location, a chip enable terminal to which is applied a chip enable signal during which a read operation or write operation is performed, memory content holding power supply terminal to which a power supply voltage is normally applied to hold memorized content of memory chips and a read/write power supply terminal to which a power supply voltage necessary for read/write operation is applied;

    a power supply connected to the memory content holding power supply terminal of each of said memory chips;

    bus means for transferring an address signal including a first part signal designating a memory location of said memory chips and a second part signal for selecting one of said memory chips;

    processor means for producing first and second data transfer control signals each taking successively a first voltage level and a second voltage level and specifying a first memory addressing state in which the first and second control signals are at the first voltage level, a second read/write operation execution state in which one of the first and second control signals is at the first voltage level and the other is at the second voltage level and a third idle state in which the first and second control signals are at the second voltage level, said states following in succession during a read or write cycle;

    means connected to said bus means and responsive to the first state of the first and second control signals to apply the first part signal of said address signal to the address terminals of each of said memory chips and responsive to the second state of the control signals to apply the chip enable signal and the read/write control signal respectively to the chip enable terminal and the read/write control terminal of each of said memory chips; and

    means responsive to the first and second states of the first and second control signals and the second part signal of the address signal to couple said power supply to the read/write operation power supply terminal of a memory chip selected by the address signal only during the first and second states of the first and second control signals.

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