Method of manufacturing intergrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques

• US 4,153,487 A
• Filed: 08/05/1977
• Issued: 05/08/1979
• Est. Priority Date: 12/27/1974
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Electric Co., Ltd. (Toshiba Corporation)
• Original Assignee: Tokyo Shibaura Electric Co., Ltd. (Toshiba Corporation)
• Inventors: Shinozaki, Satoshi, Nakamura, Junichi, Nakai, Masanori, Ito, Shintaro, Nishi, Yoshio, Tokumaru, Yukuya
• Primary Examiner(s): Dean, R.
• Assistant Examiner(s): Saba, W. G.
• Application Number:
  US05/822,194
• Time in Patent Office: 641 Days
• Field of Search: 148/175, 148/187, 148/188, 357/35, 357/36, 357/44, 357/46, 357/92, 29/576-578
• US Class Current: 438/325
• CPC Class Codes: H01L 21/033 comprising inorganic layers
• CPC Class Codes: H01L 21/8226 comprising merged transistor logic or integrated injection logic
• CPC Class Codes: H01L 27/0233 Integrated injection logic structures [I2L]

Abstract

A P type semiconductor layer is formed on an N type semiconductor layer by vapor epitaxial growth technique, an insulating film is formed on the P type semiconductor layer and a grid shape first opening is provided through the insulating film. Then, phosphorus is diffused into the P type semiconductor layer through the grid shape opening to form a first N type region extending through the semiconductor layer to reach the N type semiconductor layer. Then, second openings are formed through respective sections of the insulating film divided by and surrounded by the grid shape first opening and boron is diffused through the first and second openings to form first and second P type regions in the grid shape first N type region and the P type semiconductor layer, respectively. Finally, third openings are formed through respective portions of the insulating film and phosphorus is diffused into the P type semiconductor layer through the third openings to form second N type regions thereby forming an integrated injection logic semiconductor device including a lateral PNP transistor and a vertical NPN transistor.

Claims

1. A method of manufacturing an integrated injection logic semiconductor device in a selected portion of a semiconductor layer comprising the steps of forming the semiconductor layer of the opposite conductivity type on a semiconductor substrate of one conductivity type;

forming an insulation film on said semiconductor of the opposite conductivity type;

forming first, second and third openings through said insulation film;

doping an impurity of said one conductivity type through said first opening thereby forming a first one conductivity type region;

doping an impurity of the opposite conductivity type into said semiconductor layer of said opposite conductivity type through said first and second openings in an oxidizing atmosphere thereby forming first and second opposite conductivity type regions respectively completely within said first one conductivity type region and in said selected portion of said semiconductor layer of the opposite conductivity type; and

doping an impurity of said one conductivity type into said selected portion of the semiconductor layer of the opposite conductivity type through said third opening in an oxidizing atmosphere thereby forming a second one conductivity type region in said semiconductor layer.

2. The method according to claim 1 wherein said step for forming said first one conductivity type region comprises the steps of applying a silicon nitride film on the surface portions of said semiconductor layer of the opposite conductivity type exposed by said first, second and third openings and on said insulation film;

forming a silicon oxide film incorporated with an impurity of said one conductivity type on said silicon nitride film;

removing by photoetching technique portions of said silicon oxide film except those confronting said second and third openings;

removing the portions of said silicon nitride film with an etching solution by utilizing the remaining portion of said silicon oxide film not removed by said photoetching technique as a mask thereby exposing again said first opening;

removing the portions of said silicon oxide film on the remaining portion of said silicon nitride film thereby exposing said portion of said silicon nitride film;

applying a second silicon oxide film onto the exposed portion of said silicon oxide film, the surface portion of said semiconductor layer of the opposite conductivity type exposed again through said first opening and onto said insulation film; and

diffusing the impurity of said one conductivity type contained in said second silicon oxide film into said semiconductor layer of the opposite conductivity type by treating the assembly thus obtained with a high temperature nonoxidizing atmosphere, and wherein said step for forming said first and second opposite conductivity type regions comprises the steps of removing the portions of said second silicon oxide film except those portions thereof confronting said third opening thereby exposing again said first opening;

removing the portions of said silicon nitride film with an etching solution by using the remaining portion of said silicon oxide film as a mask thereby exposing again said second opening, and diffusing said impurity of the opposite conductivity type into said first one conductivity type region and said semiconductor layer of the opposite conductivity type through said exposed first and second openings.

3. A method of manufacturing an integrated injection logic semiconductor device in a selected portion of a semiconductor layer comprising the steps of forming the semiconductor layer of the opposite conductivity type on a semiconductor substrate of one conductivity type;

forming an insulation film on said semiconductor layer of the opposite conductivity type;

forming first, second and third openings through said insulation film;

doping an impurity of said one conductivity type into said semiconductor layer of the opposite conductivity type through said first opening thereby forming a first one conductivity type region;

doping an impurity of the opposite conductivity type into said semiconductor layer of said opposite conductivity type through said first and second openings in an oxidizing atmosphere thereby forming first and second opposite conductivity type regions respectively completely within said first one conductivity type region and in said selected portion of said semiconductor layer of the opposite conductivity type; and

doping an impurity of said one conductivity type into said selected portion of the semiconductor layer of the opposite conductivity type through said third opening in an oxidizing atmosphere thereby forming a second one conductivity type region in said semiconductor layer.

4. The method of manufacturing an integrated injection logic semiconductor device according to claim 8 wherein said step for forming said first region of the one conductivity type comprises the steps of applying a silicon nitride film on the surface portions of said semiconductor layer of the opposite conductivity type exposed by said first, second and third openings and on said insulation film;

forming a silicon oxide film incorporated with an impurity of the one conductivity type on said silicon nitride film;

removing by photoetching technique said silicon oxide film except the portions overlying said second and third openings;

removing portions of said silicon nitride film with an etching solution by utilizing the portions of said silicon oxide film overlying said second and third openings as a mask and thereby exposing said first opening;

removing the portions of said silicon oxide film overlying said second and third openings thereby exposing the remaining portion of said silicon nitride film;

applying a second silicon oxide film incorporated with an impurity of the one conductivity type onto the remaining portion of said silicon nitride film the exposed portions of the insulation film, and the surface portions of said semiconductor layer of the opposite conductivity type exposed by said first openings; and

diffusing the impurity of the one conductivity type incorporated in said second silicon oxide film into said semiconductor layer of the opposite conductivity type in a high temperature nonoxidizing atmosphere.

5. The method of manufacturing an integrated injection logic semiconductor device according to claim 4 wherein said step for forming said first and second opposite conductivity type regions comprises the steps of removing said second silicon oxide film except the portions thereof overlying said third opening thereby exposing said first opening;

removing the portions of said silicon nitride film except for the portion overlying said third opening with an etching solution by using the remaining portion of said second silicon oxide film as a mask thereby exposing said second opening, and diffusing said impurity of the opposite conductivity type into said first one conductivity type region and said semiconductor layer of the opposite conductivity type respectively through said exposed first and second openings.

6. The method of manufacturing an integrated injection logic semiconductor device according to claim 3 wherein said first opening is formed in an annular configuration and said second and third openings are formed within the area circumscribed by said first annular opening.

7. The method of manufacturing an integrated injection logic semiconductor device according to claim 3 wherein said first opening is formed in a grid shape thereby dividing said insulation film into a plurality of sections and said second and third openings are formed within each of said sections of said insulation film.

8. The method of manufacturing an integrated injection logic semiconductor device according to claim 3 which further includes the steps of reopening said first, second and third openings and forming electrode films on said first and second regions of the opposite conductivity type and on said second region of the one conductivity type region through the respective openings.