Method and arrangement for the redundancy-reducing coding of pictures

• US 4,155,097 A
• Filed: 08/18/1977
• Issued: 05/15/1979
• Est. Priority Date: 09/07/1976
• Status: Expired due to Term

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Lux, Peter
• Primary Examiner(s): Richardson, Robert L.
• Assistant Examiner(s): Coles, Edward L.
• Application Number:
  US05/825,665
• Time in Patent Office: 635 Days
• Field of Search: 358/133, 358/135, 358/138, 358/260
• US Class Current: 375/240.24
• CPC Class Codes: H04N 19/527 Global motion vector estimation
• CPC Class Codes: H04N 19/86 involving reduction of coding artifacts, e.g. of blockiness

Abstract

With known methods for predictive decorrelation it always applies only to one or more previously scanned elements of the same picture line. A disturbance for a decorrelated value leads on reconstruction to a "falsification" of a longer picture sequence. A protection from errors by check bits for each decorrelated element would considerably increase the redundancy. In accordance with the invention the picture to be scanned is divided into sub-pictures and in each sub-picture some substantially uniformly distributed elements are decorrelated as supporting positions and transmitted faultlessly, the remaining intermediate elements being decorrelated only with respect to the supporting positions of the sub-picture and transmitted without protection against errors. Consequently, the increase in redundancy by means of check bits is limited and an error with a transformed value of an intermediate element disturbs on reconstruction only that intermediate element itself and not the surrounding elements. With an arrangement for the decorrelation a number of picture lines corresponding to the number of lines a sub-picture comprises is intermediately stored and two processing circuits are connected to each time the last stages of these shift registers, one of these processing circuits decorrelating the supporting positions and the other one the intermediate elements.

Claims