Apparatus for digital data synchronization

• US 4,158,748 A
• Filed: 06/27/1977
• Issued: 06/19/1979
• Est. Priority Date: 06/27/1977
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: En, John
• Primary Examiner(s): Griffin, Robert L.
• Assistant Examiner(s): Bookbinder, Marc E.
• Application Number:
  US05/810,249
• Time in Patent Office: 722 Days
• Field of Search: 340/146.1 D, 325/38 R, 325/58, 179/15.55 T, 178/68, 178/69.1
• US Class Current: 375/368
• CPC Class Codes: H04L 7/048 using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal

Abstract

A system, including an encoder and decoder, for the transmission of digital information over a transmission medium. The encoder processes a data stream of length M and generates a transmission bit stream. The processing includes combination of the M data bits with N predetermined sync bits, via a modulo-2 adder. The resulting transmission stream has a total length less than M+N, thereby substantially minimizing the number of bits otherwise required.

The decoder regenerates the data bit stream by modulo-2 subtraction of the transmission bit stream with said N sync bits, stored within the decoder.

The resulting system thereby provides optimum synchronization and, therefore, data recovery, while requiring a minimum of transmission bits.

Claims

1. A digital communication system for processing a data bit stream having a length M, said bit stream including a predetermined initial identification bit sequence, the system comprising:

encoder means for encoding said data bit stream including;

encoder bit storage means having N predetermined sync bits stored therein;

combining means for predeterminedly combining said N sync bits with said M data bits to thereby produce a transmission bit stream having a bit length less than M+N;

decoder means for decoding said transmission bit stream including;

decoder sync bit storage means having said N predetermined sync bits stored therein;

processing means for predeterminedly processing said transmission bit stream with said N sync bits to thereby regenerate said data bit stream;

identification bit storage means having said initial identification bit sequence stored therein; and

detector means for comparing the regenerated data bit stream with the contents of said identification bit storage and producing a detect indication output responsive to a predetermined minimum correlation therebetween to allow passage of the remainder of the regenerated bit stream to an output terminal.

2. The system of claim 1 wherein the combining means is comprised of a modulo-2 adder for modulo-2 adding said M data bits with said N sync bits and wherein the processing means comprises a modulo-2 subtractor for modulo-2 subtracting said N sync bits from the transmission bit stream.