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Complementary-FET driver circuitry for push-pull class B transistor amplifiers

  • US 4,159,450 A
  • Filed: 05/22/1978
  • Issued: 06/26/1979
  • Est. Priority Date: 05/22/1978
  • Status: Expired due to Term
First Claim
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1. An amplifier comprising:

  • a p-channel field effect transistor and an n-channel field effect transistor, each having respective gate and source and drain electrodes and having a complementary drain current versus source-to-gate potential characteristic to that of the other;

    an input signal terminal at the interconnected gate electrodes of said p-channel and n-channel field effect transistors;

    means applying relatively positive and relatively negative operating potentials to the source electrode of said p-channel field effect transistor and to the source electrode of said n-channel field effect transistor, respectively;

    means for applying a biasing potential to said input signal terminal, which biasing potential is substantially midway between said relatively positive and relatively negative operating potentials, which includes means for direct coupling each of the drain electrodes of said p-channel and n-channel field effect transistors to said input signal terminal;

    first and second output transistor means of complementary conductivity types to said p-channel field effect transistor and to said n-channel field effect transistor, respectively, each having input and output and common electrodes;

    means connecting the drain electrode of said p-channel field effect transistor to the input electrode of said first output transistor means applying the drain potential of said p-channel field effect transistor to the input electrode of said first output transistor means;

    means connecting the drain electrode of said n-channel field effect transistor to the input electrode of said second output transistor means for applying the drain potential of said n-channel field effect transistor to the input electrode of said second output transistor means;

    means connected between the input electrodes of said first and second output transistor means for biasing them so that said first output transistor means is non-conductive during substantial negative excursions of output signal and so that said second output transistor means is non-conductive during substantial positive excursions of output signal;

    means for applying relatively positive and relatively negative operating potentials to the output electrode of said first output transistor means and to the output electrode of said second output transistor means, respectively; and

    an output signal terminal between the common electrodes of said first and second output transistors means, respectively.

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